Semiconductor power device having walls of an inverted mesa shap

Details Semiconductor power device having walls of an inverted mesa shap Semiconductor power device having walls of an inverted mesa shap

1992-03-03

1994-05-17

Carroll, J.

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

With peripheral feature due to separation of smaller...

257339, 257496, 257586, 257622, 257623, 257625, 257626, H01L 2906

Patent

active

053130928

ABSTRACT:
A semiconductor device of vertical arrangement includes an anode region formed of a first semiconductor substrate and a second semiconductor substrate joined with the first semiconductor substrate. The first semiconductor substrate forms a high-resistance layer with a predetermined impurity density, and the second semiconductor substrate forms a low-resistance layer whose impurity density is higher than that of the high-resistance layer. A PN junction is formed inside the first semiconductor substrate. The periphery of the first semiconductor substrate including the PN junction is configured in an inverted mesa structure and coated with an insulation material. With this arrangement, the semiconductor device has a high withstand voltage and enables an employment of a large diameter wafer.

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S. M. Sze, Semiconductor Process, Physics and Technology, John Wiley & Sons, New York (1985) p. 456.

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