Semiconductor power device and method of formation

Details Semiconductor power device and method of formation Semiconductor power device and method of formation

2001-11-30

2003-11-11

Meier, Stephen D. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S750000, C257S762000

Reexamination Certificate

active

06646347

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to semiconductor manufacturing, and more particularly to a MOS power device and its method of fabrication.
BACKGROUND OF THE INVENTION
One technique for fabricating high-power metal oxide semiconductor (MOS) devices uses a thick metallization (power metal) formed over the semiconductor device to provide current to the semiconductor device circuitry. Power metal has been effective in reducing on-resistance (Ron), eliminating non-uniform switching, increasing thermal capacity, forming spiral inductors, and improving the current carrying capacity and electromigration reliability of semiconductor devices.
FIG. 1
is an illustration of a prior art power metal structure that includes power metal structures
9
A and
9
B. The power structures
9
A and
9
B include a thick copper film
9
, a seed layer
8
, and an adhesion/barrier layer
7
formed over a passivation layer
6
. The power metal structures
9
A and
9
B electrically connect to the semiconductor device through pad openings
10
,
11
, and
12
via interconnects
3
,
4
, and
5
. As illustrated with respect to interconnect
2
, which has no pad opening, not all interconnects electrically contact the power metal structures. Thus, portions of passivation layer
6
overlying interconnect
2
also function to electrically isolate the interconnect
2
from the power metal structure
9
A.
However, residual film stress and coefficient of thermal expansion (CTE) differences between the passivation layer
6
and the power metal structure
9
A can result in shear stress between the power metal structure
9
A and passivation layer
6
. A shear stress that exceeds fracture strength of the passivation layer
6
can produce cracks or defects X in the passivation layer
6
, which can cause electrical shorting between the interconnect
2
and the power metal structure
9
A. Under extreme conditions, the shear stress can also produce lateral shear of underlying interconnect
2
. The shear stress results from contraction of power copper structures, as indicated by the vectors A
1
, A
2
, A
3
and A
4
. The force of the stress is highest at the edge regions of the power metal structures
9
A and
9
B and decreases toward central regions of the power metal structures
9
A and
9
B. Some defects are detectable after reliability stressing and, depending on the defect's severity, may be detectable at burn-in or final test, in which case yield is impacted. If a defect goes undetected, it poses a risk as an in-the-field failure and becomes a reliability issue. One prior art method to reduce the power metal induced shear stress is to reduce the thickness of the power metal film. This, however, is undesirable because it can negate the previously discussed power metal's advantages.


REFERENCES:
patent: 5744843 (1998-04-01), Efland et al.
patent: 6066877 (2000-05-01), Williams et al.
patent: 6093966 (2000-07-01), Venkatraman et al.
patent: 6140702 (2000-10-01), Efland et al.
patent: 6150722 (2000-11-01), Efland et al.

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