Semiconductor planarization process and structures made thereby

Details Semiconductor planarization process and structures made thereby Semiconductor planarization process and structures made thereby

1983-02-03

1985-09-10

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29571, 29576W, 156657, 156662, 357 49, H01L 2195

Patent

active

045397449

ABSTRACT:
A silicon substrate having a silicon dioxide bird's head is provided. A thermal oxide layer is grown on the exposed silicon surface. A layer, e.g., 4000 A.degree., of phosphogermanosilicate glass is deposited on the thermal oxide and on the silicon dioxide bird's head. The structure is heated to 950.degree. C., causing a reflow of the glass which results in a planar surface. The thermal oxide and the phosphogermanosilicate glass are then wet etched at the same rate with a solution of hydrofluoric acid, ammonium fluoride, and deionized water. The wet etch is terminated when the exposed silicon surface is reached, resulting in a smooth surface as defined by the planar reflow surface. Other embodiments are disclosed.

REFERENCES:
patent: 4073054 (1978-02-01), Kaji et al.
patent: 4417914 (1983-11-01), Lehrer
Tenney, A. S. et al., "Etch Rates of Doped Oxides in Solutions of Buffered HF", in J. Electrochem. Soc., 120 (8), pp. 1091-1095, 8-1973.

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