Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2001-06-26
2003-10-28
Karlsen, Ernest (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB, C714S046000
Reexamination Certificate
active
06639417
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor testing apparatus and, more particularly, to a semiconductor parametric testing apparatus for measuring several parameters for semiconductors on a wafer and testing them in, for example, the process for manufacturing semiconductor integrated circuits.
2. Description of the Related Art
One of the purposes of a semiconductor parametric tester is to test wafers in the process for manufacturing semiconductor circuit devices. An example of a semiconductor parametric tester used for this purpose will now be described with reference to
FIG. 6. A
semiconductor parametric testing system
1
comprises a tester body
3
for providing electric signals to a wafer
2
to be tested and measuring electric signals from the wafer
2
, a wafer prober
5
for taking the wafer
2
out of a wafer lot
4
and putting its probe on a predetermined die, a computer
6
A for controlling the tester body
3
and wafer prober
5
and processing measured data, and a measuring program group
6
B for operating the computer
6
A.
The measuring program group
6
B comprises: a test plan
7
consisting of information files regarding the wafer
2
, devices on it, and the like; a measuring algorithm
8
consisting of files for defining a measuring algorithm; a core program
9
for initializing each section, loading and executing the test plan
7
and measuring algorithm
8
; and a limit file
10
. Furthermore, the measuring program group
6
B includes a user interface program
9
a
for accepting input information from an operator and outputting information to him/her via a display and keyboard. Each of the test plan
7
, measuring algorithm
8
, and limit file
10
includes, for example, a fill-in-the-box builder for enabling a user to create a file easily.
The test plan
7
includes wafer specifications
7
a
for defining the attributes, such as the name and location, of a die on a wafer, die specifications
7
b
for defining the name and location of a module on a die, probe specifications
7
c
for defining a method for connecting device pads on a probe card and switching matrix pins, and test specifications
7
d
for defining a measuring algorithm used for a device test.
The definitions of terms used in this specification are as follows. With reference to
FIG. 7
, the wafer
2
is a group of a plurality of dice
20
on one substrate. The die
20
is a group of modules
21
consisting of a plurality of electronic devices. The module
21
, being a group of electronic devices, is the largest unit that can be probed at a time. The wafer prober
5
puts its probe on each module
21
, and measurement will be performed by the tester body
3
. An electronic device is a unit element, such as a resistor, MOSFET, or other transistor. The wafer lot
4
is the unit for several wafers that can be mounted on the wafer prober
5
at a time. The wafer prober
5
is connected physically and electrically to the wafer
2
, and the tester
3
, being a program set, performs necessary measurements. The software called test shell
22
coordinates them. The test shell
22
consists of framework
23
and the test plan
7
. As shown in
FIG. 8
, the framework
23
is a program in which processes necessary for testing and a user interface at the time of performing tests are described. As stated above, the contents of a test performed on the wafer
2
are described in the test plan
7
.
With reference to
FIG. 8
, the contents of the framework
23
include the processes of setting an environment for performing a test (
24
), performing the test (
25
), and outputting test results (
26
). At the time of performing a test, an operation panel
28
for operation corresponding to these processes will be displayed as a user interface. The user interface for setting an environment for performing a test (
24
) enables an operator to set the parameters regarding the wafer prober
5
, the operational procedure after judging measurement results, the manner of outputting a report, the contents of measured values displayed at the time of performing a test, the procedure for operating an test environment before performing a test, etc. At the time of performing a test
25
, the contents of instructions given through the framework
23
are followed, control is exerted so that the wafer prober
5
puts its probe on the module
21
as described in the test plan
7
, and measurements are performed on an object to be measured. When the measurement of one module
21
is completed, the probe moves to another module to be tested next.
A user interface for outputting test results
26
enables an operator to specify whether or not another test should be performed on the basis of a judgment on the wafer measured and whether or not measurement results should be reported after performing the second test. An operation panel shown in
FIG. 9
is an example of a graphical user interface for performing the above processes dynamically at the time of executing the framework
23
. At the time of performing a test, the results of the test described in the test plan
7
and a judgment on each wafer made on the basis of certain criteria will be displayed through this interface.
When this test is being performed, it can be paused by a user's operation with any timing. However, this is done by watching an operation panel which is displayed separately from an operation panel for the framework and indicates the progress of the test and by pressing a pause button at an objective die. This method cannot define pause timing, so a pause position on a program flow (a step in a test algorithm where a test is paused) cannot be specified. In addition, an operator must continue to watch this operation panel during a test, which is very stressful task. Furthermore, the test shell does not provide any means for the operator to know a module on which the wafer prober
5
is putting its probe at that time. Therefore, physical information must be read from the wafer prober
5
in order to know where the wafer prober
5
is positioned. Moreover, if the wafer prober
5
has moved to a module not defined originally, it is difficult to return it to the original pause position, and this makes data collected so far unusable.
A breakpoint may be established in the measuring algorithm
8
or framework
23
to pause a test at a certain position. In this way, however, the program will always stop at a die
20
which has been specified as an object to be measured, then a command will be entered manually. Furthermore, a function to navigate a probe is not included, so, for example, measurement results obtained cannot be compared with those of other dice. The possible extent of failure analysis therefore is limited.
In addition, if a destructive test or the like is performed on the wafer
2
, the second measurement on the die which has been measured once is meaningless and a die set aside as a backup will have to be measured. However, such a die is not described in the test plan
7
, so no method is provided for moving the probe.
SUMMARY OF THE INVENTION
According to the present invention, there is provided a solution in response to the above-mentioned problems of the related art. An object of the present invention is to provide a semiconductor testing apparatus which makes it possible to specify a position on a wafer at which a test is paused with more accurately and easily.
The present invention provides a semiconductor parametric testing apparatus which makes it possible to specify a die and module on each wafer at which a test should be paused. Furthermore, the present invention provides a semiconductor parametric testing apparatus characterized by pausing a test at a predetermined die and module on each wafer. This allows a test to pause easily at an arbitrary module in an arbitrary die. A defective spot therefore can be found more easily and quickly.
In addition, the present invention provides a semiconductor parametric testing apparatus with which it is possible for an operator to interactive
Agilent Technologie,s Inc.
Karlsen Ernest
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