Semiconductor parallel tester

Details Semiconductor parallel tester Semiconductor parallel tester

1999-06-28

2002-11-05

Le, N. (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S754090, C324S761010, C324S537000

Reexamination Certificate

active

06476628

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to automatic test equipment for testing semiconductor devices, and more particularly a semiconductor tester capable of simultaneously testing a relatively large number of semiconductor devices in parallel.
BACKGROUND OF THE INVENTION
Semiconductor manufacturers employ a variety of different processes in the fabrication of semiconductor devices. One of the more critical processes involves electronically testing each and every chip according to predetermined criteria. This generally involves stimulating the inputs of the device to generate expected output signals, and monitoring the actual output signals to verify that the actual and expected outputs match. The test procedure is often conducted first at the wafer level to weed out devices early in the production process, and later at the packaged-device level.
To carry out the test process, semiconductor manufacturers typically utilize sophisticated machines commonly referred to as automatic test equipment (ATE) or testers. ATE designed for a production environment is often fairly costly, thereby contributing to the overall unit cost for each semiconductor device. Semiconductor manufacturers have thus realized that in order to minimize device unit costs, and remain competitive, the ATE must provide significant cost savings to warrant its high cost.
One way that ATE contributes to lower fabrication costs is by simultaneously testing groups of devices-under-test (DUTs) in parallel. This is commonly done for relatively low pin count memory devices and dramatically improves device throughput. This consequently reduces unit costs. Conventional parallel testers typically include a computer-driven test controller or mainframe unit that couples to a separately disposed testhead via a fairly large cable bundle. The bundle includes several hundred signal cables that collectively terminate in a first backplane assembly. The testhead generally includes a plurality of circuit boards that mount the pin electronics necessary to electronically interface with the pins of each DUT. Connections from the pin electronics are routed to a second backplane assembly, and carried through to individual double-sided pogo pins installed in a pogo or probe ring. The second backplane assembly is often constructed with relatively long trace patterns that tend to require sophisticated and expensive impedance control schemes in an effort to optimize signal quality.
One of the limitations in the number of DUTs that can be tested at any given time results from the construction of the probe ring. The dimensions of the probe ring is generally dependent on the size of a semiconductor wafer and the probe card that engages the wafer. Semiconductor wafers are often around 200 mm in diameter that dictates a 300-350 mm diameter probe card for signal routing purposes. The wafer, in turn, collectively comprises tens of DUTs having contact points accessible by finely tipped probes. Each signal path through the tester corresponding to a DUT contact point or “pin” must generally comprise a 50 ohm transmission line for optimal signal quality. This often involves surrounding each signal path through the probe ring with ground paths.
For example, conventional testers that test sixteen memory devices in parallel, each having around 32 pins, generally require approximately 512 signal pogo pins in the probe ring. Moreover, to ensure optimal signal quality, each signal pin is often surrounded by a plurality of ground pogo pins. However, as device pin counts and the need for higher parallelism increase, requiring more and more conventional signal and ground pogo pins positioned in the finite pogo ring, at some point the pogo density begins to degrade the 50 ohm characteristics of each signal path.
Semiconductor manufacturers that utilize complex ATE are also concerned with the expected uninterrupted operation time before the system has to “stand down.” Typically expressed as “mean time before failure”, or MTBF, this parameter plays an important role in determining unit costs. By maximizing the MTBF, more DUTs can be tested in a given period of time because of the overall increased eficiency of the testing operations.
One problem that contributes to a reduction in MTBF with conventional parallel testers involves the signal degradation caused by a faulty connection in a signal path. As noted above, conventional parallel testers that employ typical testheads utilize multiple backplane assemblies, contributing to a relatively high number of terminations and connections for individual signal paths. Generally, the more terminations and connections for a given path, the higher the probability of a failure therealong.
Another problem encountered with conventional parallel testers involves the difficulty in field troubleshooting and repairing specific signal paths. The time to repair a tester is often expressed as the “mean time to repair” (MTTR), and afects unit costs in much the same way as the MTBF. Typically, the signal path connections are often routed through various areas in the cable bundle, the respective backplane assemblies, and the pogo ring with little regard for quick troubleshooting and repair or replacement. This often results in a relatively long MTTR for a tester should a problem arise in one of the connections.
What is needed and heretofore unavailable is a parallel semiconductor tester capable of testing a large number of DUTs in parallel with minimal impact to the signal quality along each signal path. Moreover, the need exists for such a tester having a relatively high MTBF and relatively low MTTR to maximize device throughput for corresponding reductions in unit costs. The semiconductor tester of the present invention satisfies these needs.
SUMMARY OF THE INVENTION
The semiconductor parallel tester of the present invention provides the capability of simultaneously testing groups of DUTs without compromising on the signal integrity for each tester signal path. The tester also substantially improves the mean time between failures by minimizing the complexity of the signal interconnections. Further, the mean time to repair is dramatically minimized by modularizing many of the tester components.
To realize the foregoing advantages, the invention in one form comprises a semiconductor parallel tester for simultaneously testing a plurality of DUTs secured to a handling apparatus. The test system includes a system controller for initiating system test signals and a pin electronics assembly responsive to the system test signals to generate test pattern signals for application to the plurality of DUTs. The system further includes a signal interface defining a plurality of direct signal paths between the handling apparatus and the pin electronics assembly.
In another form, the invention comprises a signal interface for establishing a plurality of direct signal paths between a handling apparatus and a pin electronics assembly in a semiconductor tester. The signal interface includes a substantially circular probe ring formed with a plurality of axially opening cavities. The cavities are disposed in a spaced-apart annular configuration. The signal interface also includes a plurality of modular harness assemblies. Each of the modular harness assemblies includes respective proximal and distal ends. The proximal end includes a pogo module for nesting in one of the axially opening cavities and the distal end includes at least one connector for engaging the pin electronics assembly.
In yet another form, the invention comprises a pogo pin assembly for high-density integration in a semiconductor tester prober interface. The pogo pin assembly includes a coaxial cable having a center conductor and a shield. The shield terminates at a distal end with the center conductor projecting axially from the distal end and defining a distal tip. A pogo pin is fixed in close-spaced axial relationship to the distal tip via a pogo receptacle. An impedance compensation element couples to the cable and pogo pin.
In a further form, the invention comprises

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