Semiconductor packaging with ground plane conductor arrangement

Wave transmission lines and networks – Automatically controlled systems – With control of equalizer and/or delay network

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357 65, 357 81, 357 22, 357 79, 357 74, 357 80, 333 12, 333246, 361400, H01L 2348, H01L 2944

Patent

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048916862

ABSTRACT:
Packaging techniques are described which provide electrical, thermal, and mechanical advantages. A low-profile semiconductor package is described in which the leads are flat and are present in the same plane. The leads are arranged and positioned in order to eliminate inductance. A semiconductor die is secured to a ceramic substrate, and a plurality of bond wires are secured between the pads on the die and the leads of the package.

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