Semiconductor packaging technique yielding increased inner lead

Details Semiconductor packaging technique yielding increased inner lead Semiconductor packaging technique yielding increased inner lead

1992-08-21

1994-07-12

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

257786, H01L 2940

Patent

active

053291573

ABSTRACT:
A greater lead count for a given die area can be achieved with "certain non-square" geometries formed by the inner ends of conductive lines. These include various triangular configurations, as well as "greatly elongated" rectangular, parallelogram and trapezoidal configurations. The conductive lines may be leads of a lead frame, leads on a tape-based package, or traces on ceramic or PCB-substrate packages. The package body may be formed to have a shape similar to that of the die receiving area, and may also be provided with external pins, ball bumps or leads. A number of these "certain non-square" packages may be assembled in an electronic system on a mother board. Unpackaged "certain non-square" dies may be connected to the ends of traces on a substrate, and encapsulated to form a multi-chip module.

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W. Ward, Volume Production of Unique Plastic Surface-Mount Modules for the IBM 80-ns 1-Mbit DRAM Chip by Area Bond Techniques, IEEE, 1988, pp. 552-557.

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