Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material
Reexamination Certificate
1999-10-05
2001-07-17
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Insulating material
C257S700000
Reexamination Certificate
active
06262479
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor packaging structure, and especially to an improvement structure of a semiconductor package structure wherein a wall is formed on the substrate by molding compound.
BACKGROUND OF THE INVENTION
Recently, packaging is more and more important in microelectronic industry. The performance of package is an important factor to the effect of the other components. The factors in packaging comprise size, weight, cost, number of pins, power suffered, and the latency between chips. Thus, a preferred packaging must consider the factors of material, construction, and electric property in order to achieve the requirement of a specification by a minimum cost and to have a better reliability.
As shown in
FIG. 1
, a general semiconductor package structure with groove, for example, a packaging structure used in CCD or other photoelectric elements, is illustrated. As shown in the figure, this semiconductor package structure serves to package a photoelectric element and includes a substrate for bearing such photoelectric element, bonding wires for electrically connecting components to the substrate, a transparent cover or potting resin covered thereon for protecting packaging element.
As shown in
FIG. 1
, the substrate
100
has a groove in the middle portion thereof and a wall is formed on the periphery thereof. Traces are arranged on the substrate so that the semiconductor element packaged therein may be electrically connected to the outer circuit by bonding wires.
In general, substrates used in semiconductor package can be formed by ceramic material in order to have a preferred hermetic, or formed of industrial plastic materials, such as BT, through molding. However, ceramics are expensive, and are difficult to be finished. While substrates formed by general BT or other plastic materials with groove are difficult in developing a mold. This is not preferred for electronic industry or photoelectric industry which are developed quickly.
SUMMARY OF THE INVENTION
Therefore, the object of the present invention is to provide a semiconductor structure with a simple structural mold and a lower cost.
Therefore, the present invention provide a semiconductor packaging structure for packaging a semiconductor element comprises: a flat substrate having a chip seat and having a plurality of outer lead wires for electrically connecting the packaging element with the liner. A wall is formed by molding compound and is installed at periphery of the substrate in order to prevent the problem of mold flush in packaging. Bonding wires are connected on the element for electrically connecting the packaging element with outer devices. The liner extends inwards and outwards than the wall with a predetermined distance to prevent that a mold flush problem will induce in the wall. Therefore, in the present invention, a wall is formed by molding compound for reducing cost and increasing the flexibility in utility.
The various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawing.
REFERENCES:
patent: 4626960 (1986-12-01), Hamano et al.
patent: 5864092 (1999-12-01), Gore et al.
patent: 5998862 (1999-12-01), Yamanaka
patent: 6011304 (2000-01-01), Mertol
Pan Pacific Semiconductor Co., Ltd.
Potter Roy
Rosenberg , Klein & Lee
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