Semiconductor packaging part and method producing the same

Etching a substrate: processes – Forming or treating electrical conductor article – Forming or treating lead frame or beam lead

Reexamination Certificate

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C428S131000, C428S137000, C428S138000, C428S457000, C428S195100, C428S209000, C428S901000, C430S313000, C430S314000, C430S318000, C029S827000, C438S123000, C438S121000, C257S666000, C361S813000

Reexamination Certificate

active

06540927

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor packaging part (such as, for example, a lead frame or the like) and a method of producing it. The semiconductor packaging part is formed from a thin sheet metal and is so designed as to permit the semiconductor chip to be packaged such that its connecting terminals are connected to the prescribed position and led to the external terminals.
DESCRIPTION OF THE RELATED ART
Parts like lead frames are widely used to package semiconductors. Such semiconductor packaging parts are formed from a thin sheet metal and are so designed as to permit the semiconductor chip to be mounted such that its terminals are connected to the prescribed position and led to the external terminals.
The semiconductor packaging parts of this kind are fabricated and formed usually by stamping (with a press mold) or etching and are completed by applying an electrical plating on specific parts. This electrical plating is accomplished by using a template having holes formed therein corresponding to the specific parts desired. Unfortunately, however, this method suffers from the disadvantage of lacking accurate positioning because the plating position varies depending on its position relative to the template and also on the working precision of the semiconductor packaging part itself.
In order to solve this problem, there has been proposed a method which consists of forming, prior to plating, a resist layer by electrodeposition on the semiconductor packaging part, forming a pattern at the desired position, and finally performing plating. This proposed method, however, is also unable to provide the desired plating accuracy because the plating position is determined by the external dimensions of the patterning mask and the product.
Further, the recent technological development needs accurate plating on a small area surrounding the half-etched part (in the dimple state) on the sheet metal of the semiconductor packaging part.
This requirement cannot be met by the conventional method because the resist layer electrodeposited on the half-etched part involves problems with adhesion, uniformity, and peeling.
Moreover, recent demands for reducing the size and increasing the density of the semiconductor chip require the semiconductor packaging part to have a higher accuracy for the plating position.
SUMMARY OF THE INVENTION
The present invention has been completed in view of the foregoing. It is a first object of the present invention to provide a semiconductor packaging part that permits fine plating with a high positional accuracy for the semiconductor chip to be packaged. It is a second object of the present invention to provide a method of producing a semiconductor packaging part that permits fine plating with a high positional accuracy for the semiconductor chip to be packaged.
The above-mentioned first object of the present invention is achieved by a semiconductor packaging part formed from a thin sheet metal so as to connect connecting terminals of a packaged semiconductor chip to predetermined positions for conduction to external terminals, characterized by having: a first pair of alignment holes which are repeatedly provided along edges of the thin sheet metal at predetermined intervals in its lengthwise direction and which perform a positioning for forming a part pattern on a first resist layer provided so as to cover the thin sheet metal; pits which are formed in the thin sheet metal on the basis of the part pattern formed on the first resist layer and which set a packaging position of the semiconductor chip; a second pair of alignment holes which are provided adjacent to and inside said first pair of alignment holes in the widthwise direction and which perform a positioning for forming a plating pattern on a second resist layer provided so as to cover the thin sheet metal after the pits have been formed; and a plated layer which is applied on surfaces of the pits on the basis of the plating pattern formed on the second resist layer and which connects the connecting terminals. Further, it is preferable that the thin sheet metal is in the form of rectangular strip or hoop.
The above-mentioned second object of the present invention is achieved by a method of producing a semiconductor packaging part formed from a thin sheet metal so as to connect connecting terminals of a packaged semiconductor chip to predetermined positions for conduction to external terminals, characterized by comprising the steps of: forming a first pair of alignment holes in the continuous thin sheet metal along it edges repeatedly at predetermined intervals in its lengthwise direction; forming a second pair of alignment holes in said thin sheet metal adjacent to and inside the first pair of holes in the widthwise direction; on the basis of a part pattern formed by patterning at predetermined positions located according to the first alignment holes in a first resist layer provided so as to cover the sheet metal, forming pits, for setting a packaging position of the semiconductor chip in the thin sheet metal; and on the basis of a plating pattern formed by patterning at predetermined positions located according to the second alignment holes in a second resist layer provided so as to cover the thin sheet metal in which the pits have been formed, forming a plated layer on surfaces of the pit, to which the connecting terminals are connected. Further, it is preferable that the continuous thin sheet metal is in the form of rectangular strip or hoop.


REFERENCES:
patent: 4049903 (1977-09-01), Kobler
patent: 4259436 (1981-03-01), Tabuchi et al.
patent: 4642160 (1987-02-01), Burgess
patent: 4980219 (1990-12-01), Hiraide et al.
patent: 5580466 (1996-12-01), Tada et al.
patent: 5661086 (1997-08-01), Nakushima et al.

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