Active solid-state devices (e.g. – transistors – solid-state diode – Incoherent light emitter structure – In combination with or also constituting light responsive...
Reexamination Certificate
1998-02-18
2003-06-24
Cuneo, Kamand (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Incoherent light emitter structure
In combination with or also constituting light responsive...
C257S088000, C257S099000, C257S100000, C257S724000, C257S730000, C257S784000, C257S786000, C257S787000, C257S432000, C257S433000
Reexamination Certificate
active
06583444
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to microelectronic assemblies, and more specifically it relates to semiconductor chip packages having light sensitive or light emitting chips.
BACKGROUND OF THE INVENTION
The semiconductor chip packaging industry is a highly competitive business in which the packaging companies are waging an ongoing battle to improve the reliability and cost of packaged chips. Moreover, the electronics industry continues to demand that chip packages take up less space within electronic components. As such, it is desirable that the overall size of the packaged chips be reduced so that the same circuitry fits into smaller areas thereby allowing for more portability (size, weight, etc.) for the resulting finished electronic product and/or allowing for an increase in a product's processing power without also increasing its size.
One type of semiconductor chip package includes packages which incorporate light sensitive semiconductor devices such as integrated circuits. When packaging such light sensitive devices (referred to herein as “IC's” or “chips”), it is necessary to allow for the passage of visible or near visible light, i.e. ultraviolet (“UV”) or infrared (“IR”) light, to the surface of the packaged chip. For example, ultraviolet-erasable programmable read-only memories (“UV EPROMS”) have traditionally been manufactured using a standard lead frame type package, as shown in FIG.
1
. Typically in this type of package, a cavity is molded (as by an injection molding operation) around a lead frame and the back surface of the chip is attached to a paddle on the lead frame. The chip contacts on the face surface of the chip are then wire bonded to respective leads on the lead frame. This allows the chip assembly to be enclosed on three sides. The fourth side of the assembly is then fitted with a transparent lid made of glass or quartz so that the chip is physically protected but still capable of receiving light through the lid.
In a similar fashion, when packaging certain light emitting chips such as light emitting diodes (LED's), it is desirable to allow for the passage of visible or near visible light from a surface of the packaged chip. When manufacturing light emitting diodes, the LED's are commonly created on leadframe like structures. As shown in
FIG. 2
, an electrically conductive back surface of the chip is typically attached to an electrically conductive base on a first lead and chip contacts on a face surface of the chip are wire bonded to corresponding second leads. The base of the first lead typically has a notch within which the chip sits. The assembly is then encapsulated by using an injection molding technique. The encapsulant may form a lens on the top of the LED package to aid in the focusing of the light being emitted from the chip.
U.S. Pat. No. 4,890,383 to Lumbard et al. discloses another technique for packaging LED's which use a supporting frame or substrate as part of the package structure. As set forth in the '383 patent, the substrate comprises an electrically insulating material such as synthetic plastic. The top surface of the substrate includes a conductive pattern which defines a land area and a connection pad. A light emitting diode is mounted on the land area so that its terminal underneath is electrically and mechanically connected to the land area. The upper side of the light emitting diode is provided with a terminal which is electrically conductive and connected with the connection pad via a bonding wire.
A second conductive pattern of highly conductive material such as copper is deposited onto the rear surface of the substrate. This second conductive pattern defines a first terminal pad and a second terminal pad. The land area on the top side of the substrate is provided with an extension which is electrically connected to the terminal pad on the under side via a plated through groove having a semicircular cross-section. Similarly, the connection pad on the upper side of the substrate is provided with an extension which is electrically connected to the terminal pad on the under side via a plated through groove, which is preferably identical to the plated through groove. In this manner the two terminal pads serve as external terminals for the light emitting diode which mechanically secures modular component during surface mounting of the component. The assembly is provided with a transparent covering for protective purposes. Thus the light emitting diode and its electrical contacts including the bonding wire are sealed and encapsulated in the covering. The covering is made from clear or diffused epoxy, which provides optical characteristics.
Despite these and other efforts in the art, still further improvements in interconnection technology would be desirable. The chip packages manufactured in accordance with the prior art methods described above typically consume greater areas on a printed circuit board or within an electronic component than might otherwise be required. In addition, these particular prior art embodiments are also relatively complex and expensive.
SUMMARY OF THE INVENTION
In one embodiment of the present invention, a method of making a microelectronic package having an optoelectronic element, such as a light sensitive or light emitting semiconductor chip, includes providing a sacrificial layer having a first surface and one or more conductive pad areas. One or more conductive pads and a base may be selectively formed on the first surface of the sacrificial layer, preferably by using photolithographic techniques. In certain embodiments, the base may include a conductive material, such as an electrically conductive material. The base and pads are preferably formed using electroplating techniques, whereby the base is located within a central region defined by the conductive pads. After the base and the one or more conductive pads have been formed, the optoelectronic element is provided. The optoelectronic element may have a front face including a plurality of contacts and an optical area for receiving incoming light and a rear surface. The rear surface of the optoelectronic element may then be juxtaposed and attached to the top surface of the base by preferably using an adhesive such as a thermally conductive adhesive. Next, the contacts may be electrically interconnected with the one or more conductive pads on the sacrificial layer using wire bonding techniques. In one preferred embodiment, the wire bonding step includes providing conductive wires having first and second ends, bonding the first ends of the wires to the contacts and bonding the second ends of the wires to the conductive pads. Other elements which may be used to interconnect the contacts and the conductive pads include electroformed beam leads and tape-automated bonding leads (TAB leads). Next, a curable and at least partially transparent encapsulant is provided over the first surface of the sacrificial layer so as to encapsulate the base, the optoelectronic element and the one or more conductive pads and the encapsulant is cured. As used herein, the term “at least partially transparent” means a material that allows any amount of light to pass therethrough and includes the terms light transmissive, transparent and/or translucent. In certain preferred embodiments this term means a material transparent to one or more desired wavelengths of light. For example, the material may be transparent to certain wavelengths of light and opaque to other wavelengths of light. After the curing step the sacrificial layer is at least partially removed so as to leave the base and the one or more conductive pads exposed and/or accessible at a bottom surface of the encapsulant. The bottom surface of the encapsulant preferably defines the bottom of the package. In certain preferred embodiments the base and the one or more conductive pads protrude slightly beyond the bottom surface of the encapsulant so that the package may be readily interconnected with an external circuit element such as a PCB. In other preferr
Chambliss Alonzo
Cuneo Kamand
Lerner David Littenberg Krumholz & Mentlik LLP
Tessera Inc.
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