Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2005-02-07
2008-03-04
Cao, Phat X (Department: 2814)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C257S686000, C257S777000, C257SE23085
Reexamination Certificate
active
07338837
ABSTRACT:
An integrated circuit device package with a first part (101) having a cavity (104) to mount the chip (105), further I/O terminals (102) on the top surface and terminals (103) on the bottom surface. The chip has contact pads (107aand107b). The second part (110) of the package has bottom surface terminals (111) aligned with the chip contact pads, and bottom terminals (112) aligned with the terminals (102) of the first package part. The connections are provided by stud bumps between the chip contact pads and terminals (111), and by reflow material between terminals (102) and (112). The connector lines (109aand109b) in the second package part (110) comprise signal/power and ground layers. The layers are spaced by insulation between 10 and 50 μm thick, and the connector lines have a width less than three times the insulator thickness.
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Howard Gregory E.
Saran Mukul
Brady III Wade James
Cao Phat X
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Tung Yingsheng
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