Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
2008-04-24
2011-10-04
Williams, A (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257SE23023, C257SE21502, C257S738000, C257S778000, C257S780000, C257S781000, C257S779000, C257S772000, C257S774000, C257S668000, C257S773000, C257S684000, C257S796000
Reexamination Certificate
active
08030768
ABSTRACT:
A semiconductor package with a semiconductor chip having under bump metallizations (UBMs) on a first surface and a substrate having open vias. The substrate is attached to the semiconductor chip with the UBMs in alignment with the open vias. An encapsulant surrounds the semiconductor chip and the substrate and a conductor fills the open vias to form external package connections.
REFERENCES:
patent: 5219794 (1993-06-01), Satoh et al.
patent: 5723904 (1998-03-01), Shiga
patent: 6137185 (2000-10-01), Ishino et al.
patent: 6229209 (2001-05-01), Nakamura et al.
patent: 6236112 (2001-05-01), Horiuchi et al.
patent: 6256207 (2001-07-01), Horiuchi et al.
patent: 6653575 (2003-11-01), Armezzani et al.
patent: 6713863 (2004-03-01), Murayama et al.
patent: 7019406 (2006-03-01), Huang et al.
patent: 7071569 (2006-07-01), Ho et al.
patent: 7161370 (2007-01-01), Maruyama et al.
patent: 7335592 (2008-02-01), Kim et al.
patent: 7358117 (2008-04-01), Tan et al.
patent: 7364946 (2008-04-01), Karnezos
patent: 7375032 (2008-05-01), Seliger et al.
patent: 7381587 (2008-06-01), Japp et al.
patent: 7422978 (2008-09-01), Lee
patent: 7449363 (2008-11-01), Hsu
patent: 7498196 (2009-03-01), Lee et al.
patent: 7566834 (2009-07-01), Shimoto et al.
patent: 7675131 (2010-03-01), Derderian
patent: 7750467 (2010-07-01), Pu et al.
patent: 2001/0000927 (2001-05-01), Rodenbeck et al.
patent: 2001/0022404 (2001-09-01), Yamamoto et al.
patent: 2001/0042924 (2001-11-01), Hasegawa et al.
patent: 2002/0003299 (2002-01-01), Nakamura et al.
patent: 2002/0151164 (2002-10-01), Jiang et al.
patent: 2004/0184219 (2004-09-01), Otsuka et al.
patent: 2005/0040525 (2005-02-01), Chien
patent: 2006/0151870 (2006-07-01), Nishiyama et al.
patent: 2007/0029670 (2007-02-01), Shibayama et al.
patent: 2007/0246837 (2007-10-01), Dong
patent: 2007/0278657 (2007-12-01), Lee
patent: 2008/0006947 (2008-01-01), Akiba et al.
patent: 2008/0150159 (2008-06-01), Aberin et al.
patent: 2008/0315424 (2008-12-01), Lee et al.
patent: 2009/0057896 (2009-03-01), Su
patent: 2009/0200662 (2009-08-01), Ng et al.
patent: 2010/0159647 (2010-06-01), Ito et al.
patent: 2010/0200970 (2010-08-01), Zhang
Cheong Mary Annie
Gan Richard
Retuta Danny
Robles Roel
Sun Anthony Yi Sheng
Sughrue & Mion, PLLC
United Test And Assembly Center Ltd.
Williams A
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