Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2002-05-28
2004-08-24
Niebling, John F. (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S778000, C257S787000
Reexamination Certificate
active
06781240
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor chip package, and more particularly to a package with multiple stacked semiconductor chips and a manufacturing method of the package.
2. Description of the Related Art
As higher performance and integrated improvement of a semiconductor device are required, the size of the semiconductor chips increases, and higher surface-mounting density of a semiconductor device is demanded. A semiconductor package including a number of semiconductor chips inside, which is called a chip-stack package, can satisfy such demand. For example, semiconductor chips can be stacked in the package. Alternatively, a number of packages, each of which includes a single chip, can be stacked to increase the surface-mounting density.
The stacking of the packages may cause the increased height of the stacked packages. Further, for interconnecting the external leads (or terminals) of the packages often requires customized shaping of the leads, which is an additional process. For instance, such additional process may include reforming of the leads so that the leads of a upper package can contact the leads of a lower package, or connecting the leads using additional pins. In addition, the additional stacking process may reduce the yield of the stacked device.
However, the chip-stack package can be effective than the stacked packages in accomplishing the reduction of the total height of the stacked semiconductor chips.
FIG. 1
shows a conventional chip-stack package
10
. A lower semiconductor chip
113
is attached to the lower surface of a lead frame die pad
11
via an adhesive
12
, and an upper semiconductor chip
15
is attached to the upper surface of the die pad
11
via an adhesive
14
. The active surface of the lower chip
13
faces downward, and the active surface of the upper chip
15
faces upward. Bonding pads (or electrode pads)
2
of the upper and lower semiconductor chips
13
and
15
are electrically connected to leads (or external terminals)
16
via bonding wires
17
and
18
, respectively. The upper and lower semiconductor chips
13
and
15
and the bonding wires
17
and
18
are encapsulated by a package body
19
formed of a molding compound. In the package
10
, the upper and lower semiconductor chips
13
and
15
are mirror chips to each other, and bonding pads
2
are formed along the edges of the chips
13
and
15
.
FIG. 2
shows another known chip-stack package
20
, in which the active surfaces of chips
23
and
25
face toward the same direction. Chip
23
is attached via an adhesive
22
on a die pad
21
, and chip
25
is attached via an adhesive
24
on the active surface of the chip
23
. The lower chip
23
is larger than the upper chip
25
. Bonding pads
2
of the upper and lower chips
23
and
25
are electrically connected to leads
26
via bonding wires
27
and
28
, and are protected by a package body
29
. The upper and lower chips
23
and
25
may be different from each other, and bonding pads
2
are formed along the edges of the chips
23
and
25
.
FIG. 3
shows still another known chip-stack package
30
. A lower chip
33
, on which bonding pads
2
are formed along the edges, is attached to the lower surface of a lead frame
31
via an adhesive
32
, and an upper chip
35
, on which bonding pads
2
are formed along the center line, is attached to the upper surface of the lead frame
31
via an adhesive
34
. For electrical connection of the central pad chip
35
, an opening is formed in the central portion of the lead frame
31
. The edge pad chip
33
and the central pad chip
35
are electrically connected to the lead frame
31
via bonding wires
37
and
38
, respectively. The end portions of the lead frames are exposed through the lower surface of a package body
39
, and the end portions are connected to land type connections
36
.
In memory chips, use of the central-pad chips is preferred because a signal skew for a number of memory shell blocks can be decreased when the bonding pads are formed along the center line of the semiconductor chip. Further, as memory capacity and speed of the memory chips increase, the central-pad memory chips are preferred to the edge-pad chips. Accordingly, technology for stacking a number of central-pad memory chips is in demand.
SUMMARY OF THE INVENTION
In accordance with an embodiment of the present invention, a semiconductor package includes a first semiconductor chip, a second semiconductor chip, a substrate, and metal bumps. The first semiconductor chip has first central electrode pads disposed along a center of an active surface of the first semiconductor chip. The second semiconductor chip has second central electrode pads disposed along a center of an active surface of the second semiconductor chip and edge electrode pads disposed along an edge of the active surface of the second semiconductor chip. The metal bumps connect the first central electrode pads of the first semiconductor chip to the second central electrode pads of the second semiconductor chip. The second semiconductor chip is mounted on the substrate, and the edge pads of the second semiconductor chip are electrically connected to the substrate.
The second semiconductor chip includes a sawing region where the edge electrode pads are formed, and the edge electrode pads of the second semiconductor chip are connected to the substrate via bonding wires. The bonding wires are encapsulated by an encapsulant. External terminals are formed on the substrate so that the external terminals are electrically connected to the edge electrode pads of the second semiconductor chip.
In accordance with another embodiment of the present invention, a method of manufacturing a semiconductor package includes: preparing a first semiconductor chip having first central electrode pads; preparing a second semiconductor chip having second central electrode pads and edge electrode pads; attaching the second semiconductor chip to a substrate; connecting electrically the edge electrode pads of the second semiconductor chip to the substrate; encapsulating the connection between the edge electrode pads and the substrate; forming metal bumps on the central electrode pads of the second semiconductor chip; and stacking the first semiconductor chip on the second semiconductor chip so that the first central electrode pads of the first semiconductor chip attach to the respective second central electrode pads of the second semiconductor chip via the metal bumps.
The method further includes forming a package body which encapsulates the first semiconductor chip and the second semiconductor chip, and forming external terminals on the substrate. The central electrode pads of the second semiconductor chip are electrically connected to the edge electrode pads.
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Harness & Dickey & Pierce P.L.C.
Niebling John F.
Roman Angel
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