Semiconductor package with recessed leadframe and a recessed...

Details Semiconductor package with recessed leadframe and a recessed... Semiconductor package with recessed leadframe and a recessed...

2005-01-04

2005-01-04

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

C257S667000, C257S787000

Reexamination Certificate

active

06838752

ABSTRACT:
A semiconductor package is provided that includes a flat leadframe having front and rear faces. The leadframe includes a central platform and elongate electrical connection leads distributed around this platform. Electrical connection wires connect the chip to the front face of the leads, and encapsulation means encapsulates the chip such that the rear face of the leadframe is visible. The electrical connection leads include an inner end part and an outer end part, the rear faces of the inner and outer end parts lie in the plane of the rear face of the leadframe, and the inner and outer end parts are connected by a branch whose rear face is set back with respect to the plane of the rear face of the leadframe so as to define a rear recess. The electrical connection wires are connected to the leads on the front face of their inner end part.

REFERENCES:
patent: 4680613 (1987-07-01), Daniels et al.
patent: 6011303 (2000-01-01), Tanaka et al.
patent: 6025640 (2000-02-01), Yagi et al.
patent: 6452255 (2002-09-01), Bayan et al.
patent: 0 989 608 (2000-03-01), None
patent: 62098751 (1987-05-01), None
patent: 08306853 (1996-11-01), None
Cha, K.B. et al. Ultra-Thin and Crack-Free Bottom Leaded Plastic (BLP) Package Design,IEEE, Proceedings of the Electronic Components and Technology Conference,XP000624973, vol. Conf. 45, May 21, 1995, pp. 224-228.
French Preliminary Search Report dated Apr. 17, 2002 for French Patent Application No. 0107185.

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