Semiconductor package with passive elements

Details Semiconductor package with passive elements Semiconductor package with passive elements

2007-07-13

2010-11-16

Gurley, Lynne A (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

C257S686000, C257S685000, C257S738000, C257S626000, C257S777000, C257SE23010

Reexamination Certificate

active

07834437

ABSTRACT:
The semiconductor package includes a plate having first via patterns formed on a center portion and second via patterns formed on edge portions; a connection wiring formed on a top surface of the plate to connect at least one first via patterns to at least one second via patterns; a plurality of passive elements formed on the top surface of the plate having a connection wiring formed thereon; a semiconductor chip having a plurality of bonding pads attached to a bottom surface of the plate and electrically connected to the first via patterns; and a plurality of external connection terminals each of which being attached to each of the second via pattern on the bottom surface of the plate.

REFERENCES:
patent: 7087514 (2006-08-01), Shizuno
patent: 7184276 (2007-02-01), Hashimoto
patent: 2004/0178495 (2004-09-01), Yean et al.
patent: 2006/0283625 (2006-12-01), Yamamichi et al.
patent: 2008/0284045 (2008-11-01), Gerber et al.
patent: 2004-0071177 (2004-08-01), None
patent: 2006-0007920 (2006-01-01), None
patent: 2006-0064518 (2006-06-01), None

Affiliated with

Also associated with

Rating

Semiconductor package with passive elements does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor package with passive elements, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor package with passive elements will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4186878