Semiconductor package with enhanced chip groundability and...

Details Semiconductor package with enhanced chip groundability and... Semiconductor package with enhanced chip groundability and...

2005-06-07

2005-06-07

Smoot, Stephen W. (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

With peripheral feature due to separation of smaller...

C257S783000, C257S787000, C438S113000, C438S126000

Reexamination Certificate

active

06903441

ABSTRACT:
A semiconductor package and a fabrication method thereof are provided, in which a ground pad on a chip is electrically connected to a ground plane on a substrate by means of an electrically-conductive wall formed over a side surface of the chip and an electrically-conductive adhesive used for attaching the chip to the substrate. Therefore, a wire-bonding process is merely implemented for power pads and signal I/O (input/output) pads on the chip without having to form ground wires on the ground pads for electrical connection purposes. This benefit allows the use of a reduced number of bonding wires and simplifies wire arrangement or routability. And, a grounding path from the chip through the electrically-conductive wall and electrically-conductive adhesive to the substrate is shorter than the conventional one of using ground wires, thereby reducing a ground-bouncing effect and improving electrical performances of the semiconductor package.

REFERENCES:
patent: 5508556 (1996-04-01), Lin
patent: 5581122 (1996-12-01), Chao et al.
patent: 5990566 (1999-11-01), Farnworth et al.
patent: 6316287 (2001-11-01), Zandman et al.
patent: 6586280 (2003-07-01), Cheah
patent: 2002/0041027 (2002-04-01), Sugizaki

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