Semiconductor package with die pad having recessed portion

Details Semiconductor package with die pad having recessed portion Semiconductor package with die pad having recessed portion

2002-03-29

2004-10-26

Parekh, Nitin (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With structure for mounting semiconductor chip to lead frame

C257S666000, C257S669000, C257S787000, C257S784000

Reexamination Certificate

active

06809408

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor packages, and more particularly, to a lead-frame-based semiconductor package with a die pad that serves as a chip carrier and is formed with a through hole.
BACKGROUND OF THE INVENTION
Conventionally, a semiconductor package with a lead frame as a chip carrier is inherent with significant problems; for example, a die pad of the lead frame is relatively large in surface area, and weak in adhesion with an encapsulant that encapsulates a chip mounted on the die pad. This weak adhesion tends to cause delamination between the die pad and the encapsulant when the semiconductor package is subjected to reliability tests or temperature variation in subsequent processes, making reliability and quality of the semiconductor package adversely affected. Further, with relatively larger contact area between the die pad and the chip, during temperature cycles in fabrication processes, the chip would suffer greater thermal stress from the die pad, and easily causes chip cracking or delamination between the chip and the die pad in this conventional semiconductor package.
In order to solve the above problems, U.S. Pat. No. 5,233,222 discloses a semiconductor package with a die pad having a recessed portion. As shown in
FIG. 4A
, this semiconductor package
3
has a die pad
30
formed with a through hole
300
. A chip
31
is adhered onto the die pad
30
by silver paste
32
in a manner that, the chip
31
covers the through hole
300
, and a bottom surface
310
of the chip
31
is partly exposed out the through hole
300
. This structure greatly decreases contact area between the chip
31
and the die pad
30
, and effectively reduces thermal stress applied from the die pad
30
to the chip
31
, so as to prevent the occurrence of chip cracking or delamination between the chip
31
and the die pad
30
. Moreover, the through hole
300
formed through the die pad
30
further helps enhance adhesion between the die pad
30
and an encapsulant
33
for encapsulating the chip
31
. Similarly, U.S. Pat. No. 5,327,008 teaches a semiconductor package having an approximately X-shaped die pad, which is purposed the same function for reducing contact area between a chip and the die pad as the former U.S. patent reference, and not to be further illustrated by drawings herein.
Even with provision of several benefits as detailed above for the foregoing two U.S. patents, nevertheless, it needs to take much effort to accurately control the amount of silver paste being applied on the die pad for attaching the chip thereon. When too much silver paste is used, as shown in
FIG. 4B
, excess silver paste
32
would flash downwardly from edge of the through hole
300
of the die pad
30
, and consequently contaminate equipment and semiconductor products. On the other hand, if silver paste is not sufficiently applied, as shown in
FIG. 4C
, a gap
301
unfilled by silver paste would be left between the chip
31
and the die pad
30
nearby the through hole
300
. This gap
301
is usually around 25.4 &mgr;m (1 mil) in dimension. An encapsulating resin for forming the encapsulant
33
may have its filler size larger than 25.4 &mgr;m, and cannot fill into the gap
301
during a molding process. As such, air trapped in the gap
301
is not able to be ventilated, but forms voids in the gap
301
. The voids would easily cause cracks of the chip
31
at corresponding positions in subsequent fabrication processes. The occurrence of paste flash or void forming both detrimentally damages reliability and yield of fabricated products. Accordingly, if to precisely control the applied amount of silver paste, this would undesirably increase costs and process complexity of fabrication, but still cannot be proved to perfectly solve the problem of excess or insufficient usage of silver paste.
In response to the foregoing drawbacks, U.S. Pat. Nos. 4,942,452 and 5,150,193 respectively teach the forming of a groove on a die pad in a semiconductor package. As shown in
FIG. 5
, a die pad
40
of this semiconductor package
4
is formed with a groove
401
nearby a through hole
400
that penetrates through the die pad
40
. The groove
401
is used to retain part of silver paste
42
applied on the die pad
40
, and to prevent flash of silver paste
42
if being applied in excess. Thereby, the problem of silver paste
42
flashing into the through hole
400
can be effectively solved; however, if in provision of not enough silver paste
42
, a gap
402
would be left between a chip
41
and the die pad
40
, and forming of voids in the gap
402
is still a drawback undesirably pertained to the semiconductor package
4
.
SUMMARY OF THE INVENTION
A primary objective of the present invention is to provide a semiconductor package, which effectively prevents void forming and flashing of silver paste from occurrence.
Another objective of the invention is to provide a method for fabricating a semiconductor package, which effectively prevents void forming and flashing of silver paste from occurrence.
In accordance with the above and other objectives, the present invention proposes a semiconductor package, comprising: a lead frame having a die pad and a plurality of leads, the die pad being formed with at least a through hole and a recessed portion that dents from a top surface of the die pad and is connected to the through hole; a chip mounted on the die pad by an adhesive in a manner that, the chip covers over the through hole, and a surface of the chip is partly exposed out the through hole; a plurality of bonding wires for electrically connecting the chip to the leads; and an encapsulant for encapsulating the chip, the die pad, the bonding wires and part of the leads, wherein the recessed portion of the die pad is completely filled with an encapsulating compound used for forming the encapsulant.
Size and shape of the through hole of the die pad are not particularly limited; the die pad needs to be structured for reducing contact area between the chip and the die pad, and for firmly supporting the chip mounted on the die pad.
The recessed portion of the die pad is necessarily dimensioned in depth greater than largest filler size of the encapsulating compound used for forming the encapsulant. During a molding process, by filling the recessed portion with the encapsulating compound, air trapped in the recessed portion can be completely ventilated without causing voids formed in the recessed portion. Depth of the recessed portion is preferably made to be 1 mil, more preferably greater than 3 mils. The applied amount of adhesive is controlled as to allow a slight amount of adhesive to flash into the recessed portion, which assures contact interface between the chip and the die pad to be free of air or voids, and the adhesive is prevented from further flashing out of the recessed portion and over a bottom surface of the die pad, so that equipment and fabricated products would not be contaminated by the adhesive.
In order to further keep the adhesive in position without causing undesirable flash, a bottom surface of the recessed portion is made to slope from outward to inward; that is, depth of the recessed portion gradually decreases from inward to outward; this allows the adhesive flashing into the recessed portion to be primarily received in the deeper part of the recessed portion. Similarly, the bottom surface of the recessed portion can be formed with a groove, which further effectively helps retaining the adhesive within the recessed portion.
The recessed portion can be formed by conventional half-etching, stamping or bending techniques.


REFERENCES:
patent: 4942452 (1990-07-01), Kitano et al.
patent: 5233222 (1993-08-01), Djennas et al.
patent: 5327008 (1994-07-01), Djennas et al.
patent: 5623163 (1997-04-01), Izumi
patent: 5661338 (1997-08-01), Yoo et al.
patent: 5949655 (1999-09-01), Glenn
patent: 6274927 (2001-08-01), Glenn

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