Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
2006-02-07
2006-02-07
Schillinger, Laura M. (Department: 2813)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C438S109000, C438S465000, C438S462000
Reexamination Certificate
active
06995041
ABSTRACT:
A semiconductor package includes a substrate, a die attached and wire bonded to the substrate, and a die encapsulant encapsulating the die. The die includes a circuit side having a pattern of die contacts, planarized wire bonding contacts bonded to the die contacts, and a planarized polymer layer on the circuit side configured as stress defect barrier. A method for fabricating the package includes the steps of forming bumps on the die, encapsulating the bumps in a polymer layer, and then planarizing the polymer layer and the bumps to form the planarized wire bonding contacts. The method also includes the steps of attaching and wire bonding the die to the substrate, and then forming the die encapsulant on the die.
REFERENCES:
patent: 6097087 (2000-08-01), Farnworth et al.
patent: 6181154 (2001-01-01), Beffa
patent: 6198162 (2001-03-01), Corisis
patent: 6199743 (2001-03-01), Bettinger et al.
patent: 6235554 (2001-05-01), Akram et al.
patent: 6294825 (2001-09-01), Bolken et al.
patent: 6300687 (2001-10-01), Bertin et al.
patent: 6303981 (2001-10-01), Moden
patent: 6313522 (2001-11-01), Akram et al.
patent: 6323551 (2001-11-01), Anzai
patent: 6331453 (2001-12-01), Bolken et al.
patent: 6343019 (2002-01-01), Jiang et al.
patent: 6359334 (2002-03-01), Jiang
patent: 6372552 (2002-04-01), Kinsman et al.
patent: 6376279 (2002-04-01), Kwon et al.
patent: 6380631 (2002-04-01), Mess et al.
patent: 6385049 (2002-05-01), Chia-Yu et al.
patent: 6451624 (2002-09-01), Farnworth et al.
patent: 6465877 (2002-10-01), Farnworth et al.
patent: 6489667 (2002-12-01), Shim et al.
patent: 6501165 (2002-12-01), Farnworth et al.
patent: 6507107 (2003-01-01), Vaiyapuri
patent: 6507114 (2003-01-01), Hui et al.
patent: 6552426 (2003-04-01), Ishio et al.
patent: 6611052 (2003-08-01), Poo et al.
patent: 6638792 (2003-10-01), Hui et al.
patent: 6791168 (2004-09-01), Connell et al.
patent: 6846699 (2005-01-01), Sakurai
patent: 6908784 (2005-06-01), Farnworth et al.
patent: 2004/0009631 (2004-01-01), Connell et al.
patent: 2004/0113283 (2004-06-01), Farnworth et al.
patent: 2004/0121563 (2004-06-01), Farnwoth et al.
patent: 2004/0171191 (2004-09-01), Connell et al.
patent: 2005/0148160 (2005-07-01), Farnworth et al.
patent: 2005/0181540 (2005-08-01), Farnworth et al.
patent: 2005/0200028 (2005-09-01), Farnworth et al.
Connell Mike
Jiang Tongbi
Gratton Stephen A.
Micro)n Technology, Inc.
Schillinger Laura M.
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