Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
2005-03-15
2005-03-15
Smoot, Stephen W. (Department: 2813)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C438S126000, C438S464000
Reexamination Certificate
active
06867069
ABSTRACT:
A first adhesive tape is attached to a first major surface of a semiconductor wafer, the semiconductor wafer having a plurality of semiconductor chip regions. Protrusion electrodes are formed on a second major surface of the semiconductor wafer within the plurality of semiconductor chip regions. Portions of the semiconductor wafer located between the plurality of chip regions are removed to form a plurality of semiconductor chips. Intervals between the semiconductor chips are then expanded. Respective first major surfaces of the wiring substrates are coupled to the corresponding second major surfaces of the semiconductor chips by the protrusion electrodes to form preliminarily structures each of which is comprised of the semiconductor chip and the wiring substrate. A second adhesive tape is attached to second major surfaces of the wiring substrates. The first adhesive tape is removed from the semiconductor chips. A resin is applied to gaps between the semiconductor chips and the wiring substrates, and the second adhesive tape is removed from the wiring substrates to form the semiconductor devices.
REFERENCES:
patent: 5518964 (1996-05-01), DiStefano et al.
patent: 5670826 (1997-09-01), Bessho et al.
patent: 5817545 (1998-10-01), Wang et al.
patent: 5889332 (1999-03-01), Lawson et al.
patent: 5989982 (1999-11-01), Yoshikazu
patent: 6004867 (1999-12-01), Kim et al.
patent: 6020638 (2000-02-01), Kobayashi
patent: 6049124 (2000-04-01), Raiser et al.
patent: 6054772 (2000-04-01), Mostafazadeh et al.
patent: 6064114 (2000-05-01), Higgins, III
patent: 6094354 (2000-07-01), Nakajoh et al.
patent: 6189591 (2001-02-01), Ariye et al.
patent: 20020022301 (2002-02-01), Kwon et al.
patent: 20020068424 (2002-06-01), Hashimoto
patent: 20020168797 (2002-11-01), DiStefano et al.
patent: 5-41541 (1993-02-01), None
patent: 9-213828 (1997-08-01), None
patent: 11-307587 (1999-11-01), None
Egawa Yoshimi
Niigaki Takeshi
Shinchi Kazumi
Smoot Stephen W.
Volentine Francos & Whitt PLLC
LandOfFree
Semiconductor package with a chip connected to a wiring... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor package with a chip connected to a wiring..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor package with a chip connected to a wiring... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3369335