Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate
2000-01-12
2002-02-05
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
C257S669000, C257S672000, C257S671000, C257S670000, C257S674000, C257S678000, C257S694000, C257S698000, C438S123000, C438S112000, C438S118000
Reexamination Certificate
active
06344681
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a packaged semiconductor and a process for manufacturing the packaged semiconductor.
2. Description of the Related Art
FIG. 10
shows a conventional packaged semiconductor
10
that is, provided with a package
14
in which a semiconductor device (not shown) that is mounted on an island (not shown) and a part of a lead frame
12
(see
FIG. 7
) are sealed with a resin and a plurality of leads
12
a
extend from the side of the package
14
.
As shown in
FIG. 7
, each lead
12
a
is formed by punching the lead frame
12
. The leads
12
a
are connected to each other by tie bars A
2
and each outside lead
12
a
is connected to the lead frame
12
by a tie bar B
2
.
Dam bars (also called “tie bars”) A
1
having the function of blocking the flow of the resin during the molding of the package
14
are used to connect the leads
12
a
to each other and each lead
12
a
with the lead frame
12
. Also, the island is connected to the lead frame
12
through an island support pins
18
.
A plurality of guide holes
20
which are openings used for positioning during the process of bending the leads
12
a
are formed in the lead frame
12
. The material generally used for the lead frame
12
is a
42
alloy (Fe, Ni) or a copper alloy with a plate thickness of approximately 0.15 mm.
The surface of the molded lead frame
12
(including the lead
12
a
) is provided with solder plating through electrical connection of the lead frame
12
to an external section. In the solder plating method, shown in
FIG. 11
, the lead frame
12
and a solder electrode
11
(anode) are dipped in an acidic electrolyte
13
(solder plating bath) in which Sn and Pb have been dissolved as solder components in advance and are electrically connected to each other and energized, thereby electrodepositing solder (Sn and Pb) on the surface of the lead frame
12
(cathode).
After the solder plating is finished, the lead
12
a
is processed into a predetermined shape. Specifically, in the step of processing the lead
12
a
, as shown in FIG.
7
and
FIG. 8
, all dam bars A
1
are punched and next the tie bars B
2
at both ends are punched using a metal mold. Thereafter bending of the lead
12
a
is performed.
This bending of the leads
12
a
is carried out using a forming die
22
as shown in FIG.
9
. Namely, the lead frame
12
is automatically conveyed to and placed on a bending die
24
of the forming die
22
and an upper die
25
is allowed to descend. At this time, the pilot pin
26
mates with the guide hole
20
to position the lead frame
12
. Next, the leads
12
a
disposed in the vicinity of the package
14
are sandwiched between a knockout
28
pushed by a spring
30
and the bending die
24
. Thereafter, as shown in FIG.
8
and
FIG. 9
, the bending punch
32
is lowered so as to push down the end of each lead
12
a
, thereby performing the bending.
Next, the end portion of each lead
12
a
which includes the tie bar A
2
is cut and the island support pins
18
are cut off from the lead frame
12
to complete the manufacture of the packaged semiconductor
10
shown in FIG.
10
.
In the above bending process using a forming die, however, the solder plating on the surface of the lead is rubbed by the bending punch during the processing and the rubbed off solder plating is pressed against and laminated on the punching surface of the bending punch to create solder residue.
Moreover, this solder residue then comes off the punching surface of the bending punch during the bending of the lead and adheres again to the surface of the lead.
Consequently, the above bending causes short circuiting between the leads as well as a deteriorated appearance, giving rise to serious problems in the quality of the product.
It is therefore necessary that the operation of the apparatus be frequently suspended to clean the forming die, remarkably impairing the production efficiency of the packaged semiconductor.
SUMMARY OF THE INVENTION
In light of the above problem, an object of the present invention is to provide a packaged semiconductor produced by performing solder plating after the bending of the leads has been completed so that no solder residue is created. Another object of the present invention is to provide a process for manufacturing a packaged semiconductor. According to a first aspect of the present invention, there is provided a packaged semiconductor comprising:
a semiconductor having a plurality of leads extending therefrom, the leads having been formed by mounting the semiconductor device in a lead frame and punching and sealing the leads in the semiconductor device using a resin, wherein the leads have been bent to a predetermined configuration; and
a connector that connect the leads to the frame, the connecting means being bent substantially simultaneously as when said leads are bent to the predetermined configuration.
According to this structure, the lead frame is connected to the leads by the connecting means in the packaged semiconductor produced by punching the lead frame in order to form the plurality of leads and by mounting the semiconductor device on the lead frame and then sealing it with resin. This connector means is bent at the same time the leads are bent. Hence a connection can be maintained between the leads and the lead frame after the bending of the leads is finished.
According to another aspect of the present invention, there is provided a process for manufacturing a packaged semiconductor, comprising the steps of:
mounting a semiconductor device having leads in a lead frame by using connector to connect the semiconductor device to the lead frame;
sealing the semiconductor device using a resin;
bending the leads of the semiconductor device to a predetermined configuration and substantially simultaneously bending the connector;
dipping said lead frame and a solder electrode in an acidic electrolyte to connect said lead frame to said solder electrode electrically thereby coating the surface of said leads with solder plating; and
disconnecting the connection made by the connector.
According to this process, the packaged semiconductor provided with a package in which a semiconductor device is mounted on a lead frame in which a plurality of leads have been formed by punching and which is sealed using a resin, wherein the leads extending from the side of the package are formed by bending, is manufactured by the first to fourth steps given below.
Specifically, in the first step, the lead frame and the semiconductor device are sealed with a resin to form a package.
In the second step, the connector which connects the lead to the lead frame is bent at the same time the lead is bent.
In the third step, the lead frame and the solder electrode are dipped in the acidic electrolyte and the lead frame is electrically connected to the solder electrode to provide the surface of the lead with solder plating.
Finally, in the fourth step, the connection made by the connector is terminated.
The production of a packaged semiconductor according to the above manufacturing process ensures that since solder plating can be provided on the surface of the lead after the lead is bent, the solder plating formed on the surface of the lead does not peel off and no solder residue is produced.
According to another aspect of the present invention, there is provided a device for forming a packaged semiconductor, the device comprising:
a semiconductor having a plurality of leads extending therefrom;
a lead frame in which the semiconductor device is mounted; and
an elongated connection member having opposite longitudinal edges, with one longitudinal edge connected to the lead frame and the opposite longitudinal edge connected to a lead of the semiconductor device.
REFERENCES:
patent: 4698661 (1987-10-01), Bessonneau et al.
patent: 5528458 (1996-06-01), Yasuho et al.
patent: 5592020 (1997-01-01), Nakao et al.
patent: 5616953 (1997-04-01), King et al.
patent: 5723903 (1998-03-01), Masuda et al.
patent: 5763829 (1998-06-01), Tomita et al.
patent:
Oki Electric Industry Co. Ltd.
Rabin & Berdo P.C.
Williams Alexander O.
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