Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With separate tie bar element or plural tie bars
Reexamination Certificate
2000-10-13
2003-04-29
Cuneo, Kamand (Department: 2829)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With separate tie bar element or plural tie bars
C257S666000
Reexamination Certificate
active
06555899
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to packaged semiconductors, semiconductor packages, leadframe assemblies therefor and a method of manufacture, and more particularly, but not by way of limitation, to a semiconductor leadframe and method incorporating a reverse-down set portion in a region of the tie bar for its securement within the semiconductor package.
2. History of Related Art
It is conventional in the electronic industry to encapsulate one or more semiconductor devices, such as integrated circuit dies, or chips, in a semiconductor package. These plastic packages protect a chip from environmental hazards, and provide a method of and apparatus for electrically and mechanically attaching the chip to an intended device. Recently, such semiconductor packages have included metal lead frames for supporting an integrated circuit chip which is bonded to a chip paddle region formed centrally therein. Bond wires which electrically connect pads on the integrated circuit chip to individual leads of the lead frame are then incorporated. A hard plastic encapsulating material, or encapsulant, which covers the bond wire, the integrated circuit chip and other components, forms the exterior of the package. A primary focus in this design is to provide the chip with adequate protection from the external environment in a reliable and effective manner.
As set forth above, the semiconductor package therein described incorporates a lead frame as the central supporting structure of such a package. A portion of the lead frame completely surrounded by the plastic encapsulant is internal to the package. Portions of the lead frame extend internally from the package and are then used to connect the package externally. More information relative to lead frame technology may be found in Chapter 8 of the book
Micro Electronics Packaging Handbook,
(1989), edited by R. Tummala and E. Rymaszewski, incorporated by reference herein. This book is published by Van Nostrand Reinhold, 115 Fifth Avenue, New York, N.Y.
Once the integrated circuit chips have been produced and encapsulated in semiconductor packages described above, they may be used in a wide variety of electronic appliances. The variety of electronic devices utilizing semiconductor packages has grown dramatically in recent years. These devices include cellular phones, portable computers, etc. Each of these devices typically include a motherboard on which a significant number of such semiconductor packages are secured to provide multiple electronic functions. These electronic appliances are typically manufactured in reduced sizes and at reduced costs, which results in increased consumer demand. Accordingly, not only are semiconductor chips highly integrated, but also semiconductor packages are highly miniaturized with an increased level of package mounting density.
According to such miniaturization tendencies, semiconductor packages, which transmit electrical signals from semiconductor chips to motherboards and support the semiconductor chips on the motherboards, have been designed to have a small size. By way of example only, such semiconductor packages may have a size on the order of 1×1 mm to 10×10 mm. Examples of such semiconductor packages are referred to as MLF (micro leadframe) type semiconductor packages and MLP (micro leadframe package) type semiconductor packages. Both MLF type semiconductor packages and MLP type semiconductor packages are generally manufactured in the same manner.
In further description of the above-described semiconductor package in
FIG. 1
, the leadframe
10
is therein shown. The leadframe
10
comprises a plate type body
12
typically formed of metal and constructed with tie bars
14
extending from each of four corners surrounding a chip paddle
16
adapted for supporting an integrated circuit die also referred to as a “chip.” The chip is not shown in this particular view for purposes of illustration and will be discussed below. Along and at a distance away from the circumference of the paddle
16
, a plurality of internal leads
18
are radially formed on the leadframe body
12
. From the internal leads
18
, external leads
22
are extended with their terminals being connected to the frame body
12
. With connection to the frame body
12
, dam bars
20
are provided between the internal leads
18
and the external leads
22
in order to prevent an encapsulation material from flowing over the external leads
22
upon encapsulating and to firmly fix the internal leads
18
and the external leads
22
to the frame body
12
. The dam bars
20
, the external leads
22
, predetermined areas of the tie bars
14
, and the frame body
12
are all removed in a subsequent singlulation process. A large number of this type of leadframes
10
may be formed in a larger frame body
12
in a matrix form.
Along the periphery of the sides of the chip paddle
16
and at the ends of the internal leads directing to the chip paddle
16
, there are formed half-etched parts
15
which will be shown and discussed below.
Referring now to
FIG. 2
, there is shown a side elevational cross-sectional view, of a semiconductor package
100
, taken along the line
2
—
2
of the leadframe illustrated in
FIG. 1
, for purposes of reference. It may be seen in this view that a deep half-etched part
15
is formed in the underneath side of the tie bar
14
along a predetermined area near the internal leads
18
and at the corner of the chip paddle
16
. Generally, this and the other half-etched parts discussed herein are formed by a chemical etching process. This chemical etching process is usually conducted after a general design of the leadframe
10
is completed. As well known, areas in which the half-etched parts, such as tie bar region
15
, are to be formed remain uncoated with photoresist while the other areas are coated with photoresist before an etchant is applied to the leadframe
10
. In the body
12
which is formed in a fabrication process later, paddle
16
and the internal leads from seceding from the body
12
horizontally or vertically or making lengthy a passage through which moisture can permeate the chip, so as to restrain the moisture absorption to the semiconductor package. In addition, the half-etched parts
15
formed in the tie bars
14
interlock the chip paddle
16
and the tie bars with the body
12
. When mounting the semiconductor package
100
onto a motherboard by use of the leadframe
10
, the half-etched parts
15
allow the internal leads
18
to be distant from the tie bars
14
to prevent the internal leads
18
and the tie bars
14
from forming a short circuit through the solder that is applied. This will be described in more detail below.
Still referring to
FIG. 2
, the package
100
, as shown herein, includes an integrated circuit chip
102
mounted to the chip paddle
16
. An encapsulation material
105
has been poured over the chip
102
and leadframe
10
to form a semiconductor package body
128
. It may also be seen that the encapsulation material
105
is also present within the recesses formed by the half-etched parts
15
formed in the tie bars
14
. The semiconductor package
100
, as shown herein, comprises the semiconductor chip
102
described above, having a plurality of bond pads
112
(shown in
FIG. 3
) disposed around the circumference of the upward surface of the chip
102
, and a chip paddle
16
which is bonded to the bottom surface of the semiconductor chip
102
via a conventional adhesive.
Referring now to
FIG. 3
, there is shown the semiconductor package
100
in a side-elevational cross-sectional view illustrating other aspects of the assembly thereof. In this particular cross-sectional view of the semiconductor package
100
taken along lines
3
—
3
of the package
100
including the conductive wires extending from the semiconductor chip to be discussed below. The chip paddle
16
has a half-etched part
17
along the circumference of its side. At the corners of the chip paddle
16
are formed tie bars
14
which externa
Chung Young Suk
Jang Sung Sik
Yee Jae Hak
Amkor Technology Inc.
Cuneo Kamand
Geyer Scott
Stetina Brunda Garred & Brucker
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