Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Patent
1995-10-02
1999-04-06
Hardy, David B.
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
257700, 257701, 257750, 257758, 257760, 257773, 257780, 257786, 257766, H03L 23528
Patent
active
058922733
ABSTRACT:
A semiconductor chip having a semiconductor substrate, a plurality of pads formed above the semiconductor substrate a first passivating film formed over an entire surface of the semiconductor substrate, and having openings above the pads the surface of the first passivating film being flat, a plurality of interconnection lines formed on the surface of the first passivating film, a second passivating film formed over the entire surface of the first passivating film and having through holes, the through holes being arranged in the form of an array, the surface of the second passivating film being flat, a plurality of contacts for connection to external leads each of the contacts being formed within and above a respective one of the through holes, the contacts being arranged in the form of an array.
REFERENCES:
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patent: 5220199 (1993-06-01), Owada et al.
patent: 5309024 (1994-05-01), Hirano
patent: 5360988 (1994-11-01), Uda et al.
patent: 5457345 (1995-10-01), Cook et al.
patent: 5581122 (1996-12-01), Chao et al.
European Search Report dated Nov. 28, 1997.
Masatoshi Yasunaga et al., "Chip Scale Package* (CSP) `A Lightly Dressed LSI Chip`".
Patent Abstracts of Japan, vol. 017, No. 398; Publication No. 05074776; Mar. 26, 1993.
Aoki Hideo
Iwasaki Hiroshi
Hardy David B.
Kabushiki Kaisha Toshiba
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