Active solid-state devices (e.g. – transistors – solid-state diode – Encapsulated – With heat sink embedded in encapsulant
Reexamination Certificate
1998-10-05
2001-07-03
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Encapsulated
With heat sink embedded in encapsulant
C257S675000, C257S712000, C257S706000, C257S707000, C257S666000, C257S676000, C257S787000
Reexamination Certificate
active
06255742
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor package having low thermal resistance, and particularly to a semiconductor package incorporating a heat dispersion plate within the resin-molded portion.
2. Description of the Related Art
Explanation will first be presented with reference to
FIGS. 1A and 1B
regarding the structure of a semiconductor package having low thermal resistance of the prior art. This type of semiconductor package is of a construction in which, for example, a leadframe unit
27
is layered on heat dispersion plate
7
.
Leadframe unit
27
includes: outer leads
6
leading out of a resin-molded portion
8
; inner leads
5
extending into the resin-molded portion
8
from outer leads
6
; an island
2
, which is the mounting portion for a semiconductor element
1
; and hanging pins
4
for securing the island
2
before the resin molding process.
The semiconductor element
1
is secured by a conductive bond such as silver paste on island
2
(omitted in the figures). Electrodes (not shown in the figures) are provided on semiconductor element
1
and are connected to inner leads
5
by bonding wires
3
.
In addition, legs
15
of a heat dispersion plate
7
are formed by bending tabs provided on a circular or square thin metal plate as shown in
FIGS. 2A and 2B
. The tips of legs
15
are processed so as to be parallel to the installation surface of heat dispersion plate
7
. The reverse surface of the tips of legs
15
are exposed on the surface of a resin-molded portion
8
on the reverse side of the package after resin molding, as shown in FIG.
1
B.
Explanation is next presented with reference to
FIGS. 3A-3D
regarding the method of fabricating the above-described semiconductor package.
The operator first prepares heat dispersion plate
7
processed as described hereinabove and a leadframe
24
for which the bonding process has been completed. Heat dispersion a plate
7
is then placed in a cavity
13
of a lower die
11
of upper and lower dies that have been heated to a desired temperature as shown in FIG.
3
A. The position of heat dispersion plate
7
is controlled at this time by an inner walls
13
a
of cavity
13
such that heat dispersion plate
7
does not shift on the bottom surface of cavity
13
. A resin tablet
14
is next inserted in a transfer pot
25
.
The operator next places leadframe
24
on lower die
11
as shown in
FIG. 3B
, whereby island
2
is placed on heat dispersion plate
7
.
The operator then raises lower die
11
as shown in FIG.
3
C and closes the die such that leadframe
24
is held by lower die
11
and an upper die
10
. The closed state of the die is maintained for a prescribed time interval after closing the die to soften resin tablet
14
by the heat of lower die
11
.
After resin tablet
14
has been softened by the heat of lower die
11
, a tablet pressure plunger (not shown in the figure) rises to press the softened resin into cavities
12
and
13
and form resin-molded portion
8
as shown in FIG.
3
D.
The closed state of the die is then maintained until the resin hardens. After the resin has hardened, lower die
11
drops and an eject pin (not shown) protrudes to remove a resin-encapsulated leadframe
24
from the die.
The low-thermal resistance semiconductor package according to the foregoing description is formed by simultaneously resin-encapsulating separately constructed leadframe unit
27
and heat dispersion plate
7
as one package. However, heat dispersion plate
7
and island
2
are only in mechanical contact and no process is employed to bond the two components by a bonding material or filler. A gap may therefore occur between island
2
and heat dispersion plate
7
in the event of even slight warping in either island
2
or heat dispersion plate
7
, resulting in voids
9
(see
FIG. 1B
) after resin molding. Since the contact between island
2
and heat dispersion plate
7
is merely mechanical, moreover, the occurrence of minute gaps cannot be ruled out even if there is absolutely no warping in island
2
or heat dispersion plate
7
and both components are completely parallel.
The above-described semiconductor package of the prior art has the following problems:
First, the thermal resistance value is not significantly reduced because the thermal conductivity between island
2
and heat dispersion plate
7
is adversely affected by the formation of voids
9
between heat dispersion plate
7
and island
2
after resin molding.
A second problem is a decrease in the reliability of a package (also abbreviated as “PKG”). This decrease in reliability also occurs due to voids
9
that are formed between island
2
and heat dispersion plate
7
after resin molding as described hereinabove. Air inside these voids
9
expands due to heat in the reflow process when mounting a package on the circuit substrate, resulting in package cracks (the so-called “popcorn effect”).
A third problem is the possibility of electrical shorts caused by contact between the tips of inner leads
5
and heat dispersion plate
7
. Such shorts result from constructions that place island
2
and heat dispersion plate
7
in contact. In other words, when a leadframe lacking a dimple process (a leadframe in which the island has no down-offset toward the inner lead formation surface) is used in this package, contact may occur between inner leads
5
and heat dispersion plate
7
because there is no difference in height between island
2
and inner leads
5
.
Leadframes normally used in this construction undergo dimple processing, whereby a difference in height between inner leads
5
and heat dispersion plate
7
that is equal to the amount of dimpling can be guaranteed even if island
2
and heat dispersion plate
7
are placed in contact.
However, the amount of dimpling of the leadframe is normally on the order of 150-200 &mgr;m, meaning that a gap of only 150-200 &mgr;m can be assured between inner leads
5
and heat dispersion plate
7
, and shorts may occur between inner leads
5
and heat dispersion plate
7
in the event of shifting (floating) of heat dispersion plate
7
caused by the flow of resin when forming resin-molded portion
8
.
As a fourth problem, the extensive surfaces of the tips of legs
15
of heat dispersion plate
7
that are exposed from resin-molded portion
8
results in a decrease in the moisture resistance of the package. This problem results in part from shape of the tips of legs
15
of heat dispersion plate
7
, which are formed parallel to the installation surface of heat dispersion plate
7
.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor package that allows a decrease in the thermal resistance of a package.
Another object of the present invention is to provide a semiconductor package that is capable of preventing the occurrence of package cracks during a reflow process.
Yet another object of the present invention is to provide a semiconductor package that is capable of preventing shorts between the inner leads and the heat dispersion plate.
Still another object of the present invention is to provide a semiconductor package having improved moisture resistance.
In the semiconductor package according to the present invention, the heat dispersion plate and the semiconductor element mounting portion inside the resin-molded portion are bonded together by, for example, resin that forms the resin-molded portion, thermoplastic resin, thermosetting resin, or low-melting metal.
Thermal conductivity between the two components is therefore excellent and thermal resistance of the package can be decreased because voids are not present between the heat dispersion plate and the semiconductor element mounting portion.
In the semiconductor package of this invention, the area of head dispersion plate beyond the area of overlap with the semiconductor element mounting portion is preferably a flat portion that is offset away from the inner leads. This construction can prevent the occurrence of shorts between the inn
Foley & Lardner
NEC Corporation
Thai Luan
Thomas Tom
LandOfFree
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