Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2003-03-10
2004-12-28
Williams, Alexander Oscar (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S777000, C257S673000, C257S723000, C257S734000, C257S738000, C257S737000, C257S691000, C257S698000, C257S666000, C257S676000, C257S211000, C257S207000, C257S208000, C257S668000
Reexamination Certificate
active
06836007
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor package.
2. Description of the Background Art
With higher functionality of personal computers, memory has to be larger in capacity and faster in speed in semiconductor packages. As semiconductor packages corresponding to the increased speed, BGA (Ball Grid Array) packages are most common which require shorter interconnection distances within packages.
DRAMs (Dynamic Random Access Memory) are representative semiconductor chips used as memory. A DRAM generally has a bonding pad arranged on the center portion of the main surface of the chip. Therefore in mounting a DRAM on a substrate, the substrate is provided with an opening portion like a window frame and the DRAM is bonded on the substrate such that that part of the DRAM at which a bonding pad is arranged can be seen from this opening portion. Here, for the sake of illustration, it is assumed that DRAM is arranged on the upper side of the substrate with the bonding pad directed downward being exposed from the opening portion of the substrate. A bonding pad is also provided at the surrounding of the opening portion of the lower surface of the substrate. Through this opening portion, the bonding pad on the DRAM side is connected to the bonding pad on the substrate side using wire. Thereafter the opening portion is sealed with resin to wrap up that part of the lower surface of the DRAM at which the boding pad is arranged and the wire. The upper side of DRAM is also sealed with resin for protection. Solder balls for external connection are provided on the lower surface of the substrate. This state is generally called a BGA package.
In order to increase a memory capacity, a technique for stacking the aforementioned BGA packages may be contemplated. When two BGA packages are simply stacked to form a stacked package, a resin sealing portion for protecting a wire bonding portion is protruded on the lower surface of the upper BGA package while a resin sealing portion for protecting the DRAM body itself is protruded on the upper surface of the lower BGA package. Therefore when two BGA packages are stacked, the distance between the substrates is inevitably increased because of the heights of the resin sealing portions respectively protruding from the upper and lower substrates. When the upper and lower substrates are connected with solder balls for external connection of the upper BGA package, it becomes necessary to use a solder ball with a large diameter. To reduce the area occupied by the stacked package, the arrangement of the solder balls is preferably in a line for one side even in the case of the solder balls for connection between substrates. In one line, however, the spacing between solder balls is so narrowed that short-circuit is likely to occur. Furthermore, in the case of such a stacked package, as for the interconnection distance from the solder ball for external connection to DRAM included in each of the upper and lower BGA packages, the upper one is largely longer than the lower one thereby causing a transmission delay of a signal.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a semiconductor package that allows memory to be increased in capacity with a reduced package size as a whole, and is free from a transmission delay between upper and lower levels.
In order to attain the aforementioned object, a semiconductor package in accordance with the present invention includes: an upper substrate having an opening portion; a solder ball for connection between substrates that is arranged on a lower side of the upper substrate; a lower substrate arranged on a lower side of the solder ball for connection between substrates and having an opening portion; a solder ball for external connection connected on a lower surface of the lower substrate; a first semiconductor chip arranged on an upper surface of the upper substrate; and a second semiconductor chip arranged on a lower surface of the lower substrate. The aforementioned first semiconductor chip is electrically connected to the solder ball for connection between substrates through the opening portion of the upper substrate. The aforementioned second semiconductor chip is electrically connected to the solder ball for connection between substrates through the opening portion of the lower substrate. The aforementioned solder ball for connection between substrates is electrically connected to the solder ball for external connection.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5998860 (1999-12-01), Chan et al.
patent: 6013948 (2000-01-01), Akram et al.
patent: 6020629 (2000-02-01), Farnworth et al.
patent: 6093969 (2000-07-01), Lin
patent: 6180881 (2001-01-01), Isaak
patent: 6294825 (2001-09-01), Bolken et al.
patent: 6331453 (2001-12-01), Bolken et al.
patent: 6448640 (2002-09-01), Corisis
patent: 6507107 (2003-01-01), Vaiyapuri
patent: 6583502 (2003-06-01), Lee et al.
patent: 2001/0006258 (2001-07-01), Hur
patent: 2003/0001288 (2003-01-01), Tay et al.
patent: 2003/0006496 (2003-01-01), Vaiyapuri
patent: 2003/0197271 (2003-10-01), Corisis et al.
patent: 04-340267 (1992-11-01), None
patent: 05-82719 (1993-04-01), None
patent: 06-216182 (1994-08-01), None
patent: P2000-340737 (2000-12-01), None
Michii Kazunari
Shibata Jun
McDermott Will & Emery LLP
Renesas Technology Corp.
Williams Alexander Oscar
LandOfFree
Semiconductor package including stacked semiconductor chips does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor package including stacked semiconductor chips, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor package including stacked semiconductor chips will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3327776