Semiconductor package including stacked chips with aligned...

Details Semiconductor package including stacked chips with aligned... Semiconductor package including stacked chips with aligned...

2001-03-23

2004-07-06

Flynn, Nathan J (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S685000, C257S666000, C257S692000, C257S787000

Reexamination Certificate

active

06759737

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor package containing at least two stacked semiconductor chips.
2. Description of the Related Art
Conventionally, a stack-type semiconductor package includes a plurality of semiconductor chips that are vertically stacked one on top of the other on a leadframe substrate or a printed circuit board substrate. The stacked semiconductor chips are electrically connected to each other and to the substrate. Since the package contains a plurality of semiconductor chips, a high degree of functionality is accomplished.
A conventional stack-type semiconductor package
100
is illustrated in FIG.
1
. Package
100
of
FIG. 1
includes a printed circuit board
1
as a substrate. First circuit patterns, each including a bond finger
5
, are formed on an upper surface of a core resin layer
3
of printed circuit board
1
. Second circuit patterns, each including a land
7
, are formed on an opposite lower surface of resin layer
3
. The first and second circuit patterns are electrically connected with each other through conductive via-holes
9
that extend through resin layer
3
. A cover coat
11
formed of an insulative resin covers the upper and lower circuit patterns, except for the bond fingers
5
and lands
7
, respectively.
A first semiconductor chip
15
is bonded to a center portion of an upper surface of the printed circuit board
1
by adhesive
16
. A smaller second semiconductor chip
17
is bonded to an upper surface of the first semiconductor chip
15
by adhesive
16
.
Input and output pads
13
of the first and second semiconductor chips
15
and
17
are each connected to a respective one of the bond fingers
5
of printed circuit board
1
by conductive wires
8
. A plurality of conductive balls
20
are each fused to a respective one of the lands
7
that are formed on the lower surface of printed circuit board
1
.
The first semiconductor chip
15
, second semiconductor chip
17
, and conductive wires
8
are encapsulated in a package body
18
that is formed using an encapsulating material that is molded onto the upper surface of printed circuit board
1
.
The conventional stack-type semiconductor package
100
described above has cost disadvantages because it includes a relatively costly printed circuit board. Moreover, when package
100
is mounted on a motherboard, package
100
has a substantial mounting height above the mounting surface of the motherboard due to the combined heights of the stack of chips, the printed circuit board, the wire loops, and the conductive balls. Furthermore, because the semiconductor chips are fully enclosed by the printed circuit board and the body of hardened encapsulating material, heat generated by the semiconductor chips cannot be easily released to the outside.
SUMMARY OF THE INVENTION
Various embodiments of leadframe-based semiconductor packages for a pair of stacked semiconductor chips are disclosed. An exemplary package includes a plurality of horizontal metal leads. Each lead has a first side, an opposite second side, and an inner end. The second side of each lead includes at least one recessed horizontal surface. The inner ends of the leads face and thereby collectively define a chip placement region wherein the stack of chips is located. The chips are electrically connected to each other in a flip chip style. At least one of the chips extends over the first side of the leads and is electrically connected thereto by bond wires or other conductors such as reflowed metal balls or anisotropic conductive films. The stack of chips is encapsulated in a body of a hardened encapsulating material. The recessed horizontal surface of each of the leads is covered by the encapsulating material, and at least a portion of the second side of each of the leads is exposed as an external connector in a horizontal plane of a first exterior surface of the package body. A surface of one or both of the chips may be exposed at the exterior of the package body to facilitate heat transfer. The stack of chips may be mounted on the first side of the leads or on a chip mounting plate located in the chip placement region.
The disclosed packages provide numerous advantages over the conventional package disclosed above, including a lesser package height above a mounting surface and superior heat dissipation capabilities. In addition, by using a leadframe rather than an internal printed circuit board substrate, the cost of the package is reduced.


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