Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate
2002-01-22
2004-09-28
Williams, Alexander Oscar (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
C257S669000, C257S698000, C257S670000, C257S671000, C257S672000, C257S674000, C257S696000, C257S691000, C257S784000, C257S786000, C257S675000, C257S676000, C257S712000
Reexamination Certificate
active
06798046
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
(Not Applicable)
STATEMENT RE: FEDERALLY SPONSORED RESEARCH/DEVELOPMENT
(Not Applicable)
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor packages, and more particularly to a semiconductor package which includes leads with vertically downset inner ends.
2. Description of the Related Art
The current trend in the electronics industry is to provide electronic appliances which are multifunctional, compact, and capable of achieving high performance levels. In view of this trend, a requirement has arisen that the semiconductor packages which are used in such electronic appliances be made in a “chip size”. These chip-size packages are often referred to as a chip scale package or CSP. These chip-sized small semiconductor packages are usable in portable products such as cellular phones and PDA's which require high levels of reliability, electrical efficiency, and a small or compact size of minimal weight.
One type of currently manufactured CSP is a very small semiconductor package including a lead frame. This particular type of semiconductor package is constructed in a manner wherein a plurality of input/output signal lands (e.g. from four to one hundred signal lands) are formed at the edge of the bottom surface of the package. This package is electrically connected to a printed circuit board by soldering the lands on the bottom surface of the package. This configuration is in contrast to conventional lead frame packages which include, as an alternative to these signal lands, leads which project outwardly from the package and are formed by various trimming/forming techniques. In addition to including the signal lands formed at the periphery of the bottom surface thereof, these semiconductor packages also include a chip mounting pad, the bottom surface of which is exposed for purposes of maximizing an emission rate of heat generated by a semiconductor chip mounted thereto.
Internal to such semiconductor package is a semiconductor chip with a multitude of input/output pads. Such pads are in turn connected to leads which terminate at the signal lands. An overall limitation of the semiconductor chip design as well as the semiconductor package has been the electrical connections and configurations utilized to satisfy the required electrical inputs and outputs to and from the input/output pads. In addition, though the above-described semiconductor packages provide the small size required by the electronic appliances discussed above, they possess certain deficiencies which detract from their overall utility. One such deficiency is insufficient bonding strength between the lead frame and the remainder of the semiconductor package. The lack of adequate bonding strength makes the semiconductor package vulnerable to failure attributable to the creation of electrical discontinuities and/or the dislodging of one or more of the signal lands of the lead frame from the remainder of the semiconductor package. Accordingly, there is a need in the art for an improved semiconductor package design.
BRIEF SUMMARY OF THE INVENTION
In accordance with an aspect of the present invention, there is provided a semiconductor package which includes a chip mounting pad having a peripheral edge. The package further includes a semiconductor chip attached to the chip mounting pad. The package further includes a plurality of leads. Each lead includes an inner end and an opposing distal end. Each inner end is disposed adjacent the peripheral edge in spaced relation thereto and vertically downset with respect to each respective distal end. The package further includes at least one isolated ring structure disposed along the peripheral edge between the peripheral edge and the inner ends of the leads in spaced relation thereto. The ring structure is electrically connected to the semiconductor chip and an inner end of at least one of the leads.
Advantageously, the vertically downset nature of the inner ends of the leads (i.e., the inner ends being offset from the distal ends) tend to enhance the bonding strength of the leads with respect the overall semiconductor package. In this regard, the inner ends being vertically downset or offset enables encapsulation of the inner ends with a sealing part for securing the same internally within the semiconductor package. As such, this enhanced bonding strength tends to substantially eliminate occurrences of delamination between such sealing part and the remainder of the lead frame, such as the inadvertent dislodging of the distal ends (i.e., signal lands) from the sealing part thereby maintaining the overall integrity of the semiconductor package.
According to respective embodiments, each inner end is vertically downset with respect to each respective distal end a distance approximately equal to a thickness of the leads. The semiconductor chip includes a chip top surface and the inner ends each include an inner end top surface, and the inner end top surfaces are aligned with the chip top surface. The ring structure includes a ring top surface and the inner ends each include an inner end top surface, and the inner end top surfaces are aligned with the ring top surface. Each inner end is vertically downset with respect to each respective distal end via a die press operation. The leads each further include a lead transition section disposed between the respective inner and distal ends. The lead transition sections are angularly disposed with respect to the distal ends. The semiconductor package is contemplated to further include a sealing part which encapsulates at least the inner ends of the leads.
The present invention is best understood by reference to the following detailed description when read in conjunction with the accompanying drawings.
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Amkor Technology Inc.
Stetina Brunda Garred & Brucker
Williams Alexander Oscar
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