Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate
2001-12-26
2004-10-12
Vu, Hung (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
Reexamination Certificate
active
06803645
ABSTRACT:
STATEMENT RE: FEDERALLY SPONSORED RESEARCH/DEVELOPMENT
(Not Applicable)
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor packages, and more particularly to a semiconductor package which includes a flip chip and is specifically configured to provide a thinner profile and superior moisture resistance capabilities as compared to flip chip semiconductor packages known in the prior art.
2. Description of the Related Art
The recent trend in the electronics industry has been toward the fabrication of lighter, thinner, more simplistic and miniaturized semiconductor packages. To achieve these objectives, there has been developed semiconductor packages fabricated through the use of a flip chip bonding method wherein a semiconductor chip is electrically connected to a printed circuit board component of the package. In this flip chip bonding method, the semiconductor chip is bonded to predetermined regions of the printed circuit board component through a reflow process subsequent to the orientation of an active surface of the semiconductor chip toward the printed circuit board component. The flip chip bonding method is used as an alternative to a conventional wire bonding method wherein conductive wires are used to facilitate the electrical connection of the input and output pads of a die to a lead frame.
However, currently known semiconductor packages fabricated using the flip chip bonding method described above possess certain deficiencies which detract from their overall utility. More particularly, since such semiconductor package employs a printed circuit board component which is costly, the manufacturing cost of the entire semiconductor package is itself significantly increased. In this regard, the cost of the printed circuit board component is extremely high due to the complexity of its manufacturing process, with the printed circuit board component accounting for more than sixty percent of the total cost of the semiconductor package employing the same. As indicated above, this high cost of the printed circuit board component results in an increased cost in the semiconductor package.
Another drawback associated with the printed circuit board component is that the same typically includes a resin layer and a solder mask which each have high water absorptivity. The susceptibility of the resin layer and solder mask to high levels of water absorption causes the semiconductor package to have a low level of resistance to moisture. As a result, the life span of the semiconductor package is drastically shortened when the same is used in regions of high humidity. A further problem pertains to the conductive balls which are fused to the bottom surface of the printed circuit board component of the semiconductor package. In this regard, the conductive balls are typically thicker than the semiconductor package itself, thus resulting in a significant increase in the overall thickness of the semiconductor package assembly including the conductive balls. The present invention overcomes these and other deficiencies of prior art semiconductor packages fabricated through the use of a flip chip bonding method, as will be discussed in more detail below.
BRIEF SUMMARY OF THE INVENTION
In accordance with the present invention, there is provided a semiconductor package comprising a lead frame which includes a plurality of leads. Each of the leads defines opposed, generally planar first and second surfaces. Each of the leads is preferably half-etched so as to further define a third surface which is formed between the first and second surfaces thereof. The semiconductor package also includes a semiconductor chip which defines opposed first and second surfaces, and includes a plurality of input/output pads disposed on the first surface thereof. The input/output pads of the semiconductor chip are electrically connected to the second surfaces of respective ones of the leads via a plurality of conductive bumps. Formed on a prescribed region of the second surface of each lead is a bump land to which the corresponding conductive bump is preferably fused. Additionally, preferably applied to the entirety of the second surface of each lead with the exception of that portion or region thereof defining the bump land is a protective layer. In the semiconductor package, the semiconductor chip, the conductive bumps, and the second and third surfaces of the leads are covered by a hardened encapsulant portion. The first surfaces of the leads are exposed within the encapsulant portion so as to define input/output terminals of the semiconductor package.
The structural attributes of the present semiconductor package impart thereto the ability to withstand severe environments for prolonged durations of time. In this regard, the structure of the present semiconductor package provides substantial moisture resistance characteristics. In addition, the input/output terminals defined by the exposed first surfaces of the leads can be mounted directly to an external device such as a motherboard, thereby minimizing the thickness of the semiconductor package/motherboard assembly. The configuration of the lead frame used in the manufacture of the present semiconductor package further minimizes the cost associated with the fabrication thereof.
The present invention is best understood by reference to the following detailed description when read in conjunction with the accompanying drawings.
REFERENCES:
patent: 3838984 (1974-10-01), Crane et al.
patent: 4054238 (1977-10-01), Lloyd et al.
patent: 4530152 (1985-07-01), Roche et al.
patent: 4707724 (1987-11-01), Suzuki et al.
patent: 4756080 (1988-07-01), Thorp, Jr. et al.
patent: 4812896 (1989-03-01), Rothgery et al.
patent: 5041902 (1991-08-01), McShane
patent: 5157480 (1992-10-01), McShane et al.
patent: 5172213 (1992-12-01), Zimmerman
patent: 5172214 (1992-12-01), Casto
patent: 5200362 (1993-04-01), Lin et al.
patent: 5200809 (1993-04-01), Kwon
patent: 5214845 (1993-06-01), King et al.
patent: 5216278 (1993-06-01), Lin et al.
patent: 5221642 (1993-06-01), Burns
patent: 5258094 (1993-11-01), Furui et al.
patent: 5273938 (1993-12-01), Lin et al.
patent: 5277972 (1994-01-01), Sakumoto et al.
patent: 5278446 (1994-01-01), Nagaraj et al.
patent: 5279029 (1994-01-01), Burns
patent: 5332864 (1994-07-01), Liang et al.
patent: 5336931 (1994-08-01), Juskey et al.
patent: 5343076 (1994-08-01), Katayama et al.
patent: 5406124 (1995-04-01), Morita et al.
patent: 5424576 (1995-06-01), Djennas et al.
patent: 5435057 (1995-07-01), Bindra et al.
patent: 5474958 (1995-12-01), Djennas et al.
patent: 5521429 (1996-05-01), Aono et al.
patent: 5604376 (1997-02-01), Hamurgen et al.
patent: 5608267 (1997-03-01), Mahulikar et al.
patent: 5639990 (1997-06-01), Nishihara et al.
patent: 5640047 (1997-06-01), Nakashima
patent: 5641997 (1997-06-01), Ohta et al.
patent: 5646831 (1997-07-01), Manteghi
patent: 5650663 (1997-07-01), Parthasarathi
patent: 5683806 (1997-11-01), Sakumoto et al.
patent: 5696666 (1997-12-01), Miles et al.
patent: 5701034 (1997-12-01), Marrs
patent: 5710064 (1998-01-01), Song et al.
patent: 5736432 (1998-04-01), Mackessy
patent: 5776798 (1998-07-01), Quan et al.
patent: 5783861 (1998-07-01), Son
patent: 5835988 (1998-11-01), Ishii
patent: 5859471 (1999-01-01), Kuraishi et al.
patent: 5866939 (1999-02-01), Shin et al.
patent: 5877043 (1999-03-01), Alcoe et al.
patent: 5894108 (1999-04-01), Mostafazadeh et al.
patent: 5969426 (1999-10-01), Baba et al.
patent: 5977613 (1999-11-01), Takata et al.
patent: 5977630 (1999-11-01), Woodworth et al.
patent: 5981314 (1999-11-01), Glenn et al.
patent: 5986885 (1999-11-01), Wyland
patent: 6001671 (1999-12-01), Fjelstad
patent: 6025640 (2000-02-01), Yagi et al.
patent: 6072228 (2000-06-01), Hinkle et al.
patent: 6130115 (2000-10-01), Okumura et al.
patent: 6130473 (2000-10-01), Mostafazadeh et al.
patent: 6140154 (2000-10-01), Hinkle et al.
patent: 6143981 (2000-11-01), Glenn
patent: 6225146 (2001-05-01), Yamaguchi et al.
patent: 6229200 (2001-05-01), Mclellan et al.
patent: 6242281 (2001-06-01), M
Amkor Technology Inc.
Stetina Brunda Garred & Brucker
Vu Hung
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