Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With semiconductor element forming part
Reexamination Certificate
2001-08-18
2004-08-24
Lee, Hsien Ming (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With semiconductor element forming part
C257S687000, C257S690000, C257S787000, C438S107000, C438S108000, C438S124000, C438S455000, C438S614000, C438S617000
Reexamination Certificate
active
06781222
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor packages and fabricating methods thereof, and more particularly, to a semiconductor package having passive devices and a fabricating method thereof.
BACKGROUND OF THE INVENTION
A conventional ball grid array (BGA) semiconductor package has a plurality of solder balls implanted on a bottom surface of a substrate in an array arrangement as connectors sufficient in number for the need of the semiconductor chip with high integration encapsulated in the semiconductor package. As such a BGA semiconductor package is suitable for the use of a semiconductor chip which contains more electronic components or passive devices such as capacitors, resistors or inductors, the BGA semiconductor package becomes the mainstream for packaged products.
Passive devices, such as capacitors, resistors or inductors, can be operatively associated with semiconductor packages, for example, a high-frequency semiconductor package. For BGA semiconductor packages, the passive devices are typically disposed at corners of the substrate on which a semiconductor chip is mounted or on an additional layout area of the substrate excluding a chip-mounting region (as shown in
FIG. 1
) so as to prevent the passive devices from affecting the electrical connection between the semiconductor chip and a plurality of bonding fingers formed on the substrate. However, the foregoing arrangement for the passive devices generates several problems. First, the requirement for the passive devices to be disposed at predetermined positions on the substrate restricts the flexibility of substrate routability. Moreover, the layout number of the passive devices is limited by formation positions of the bonding fingers, which is disadvantageous for a highly integrated semiconductor chip. In addition, in the case of more passive devices being required with increase in the performance for the semiconductor package, the substrate surface needs to simultaneously adopt more semiconductor chips and more passive devices, thereby making the semiconductor package undesirably enlarged in profile.
According to the above problems, it is considered to integrate the passive devices at a region of the substrate between the semiconductor chip and a wire bonding area. However, with increase in density of the electronic components and electric circuits formed on the semiconductor chip, more bonding wires are also required; further, as the passive device is generally larger in height (0.8 mm) than that of the semiconductor chip (0.55 mm), in order to avoid the contact between the bonding wire and the passive device for preventing short circuit from occurrence, the bonding wire needs to be elongated upwardly for crossing over the passive device, as shown in FIG.
2
. This not only enhances the bonding difficulty but also increases the length of wire loop. Additionally, if the elongated bonding wire is not firmly supported, it will sag down due to gravity to contact the passive device thereby resulting in the short circuit This can be solved by U.S. Pat. No. 5,847,445 disclosing an insulative dam disposed on the substrate and the semiconductor chip for supporting the elongated bonding wire. However, this method not only makes the fabricating process more complex, but also raises the fabricating cost due to an increased amount of gold or aluminum for making the elongated bonding wires.
Furthermore, as the passive devices are attached to the predetermined positions of the substrate through a solder paste by means of conventional surface-mount technology (SMT), problems may be generated during a molding process. For example, as a molten resin is injected at a high temperature (175° C.) close to the melting temperature of the solder paste (183° C.) used for the attachment of the passive devices, the solder paste then becomes semi-melted, making the passive devices possibly dislocated from the predetermined positions due to a stress from the mold flow of the molten resin, so that the quality of conductivity is degraded and the short circuit can be induced.
SUMMARY OF THE INVENTION
A primary objective of the present invention is to provide a semiconductor package and a fabricating method thereof in which a plurality of passive devices are integrated under a semiconductor chip, so as to increase the layout number of the passive devices in the semiconductor package and enhance the flexibility of substrate routability, as well as reduce an occupied area of a substrate for miniaturize the semiconductor package in profile. Moreover, the invention has the passive devices integrated under the chip for preventing the dislocation of the passive devices caused by a high temperature and mold flow from occurrence. Furthermore, the invention having the integrated passive devices allows the wire bonding difficulty to be reduced, and the direct contact between bonding wires and the passive devices to be avoided, so as to prevent short circuit from occurrence and save the fabricating cost.
According to the above and other objectives, the invention provides a novel semiconductor package and a fabricating method thereof. The semiconductor package includes: a substrate having a device-mounting region predefined within a chip-mounting region thereon for forming a plurality of solder pads thereon, and a wire bonding region predefined around the device-mounting region for forming a plurality of bonding fingers thereon; a plurality of passive devices (such as capacitors, resistors or inductors) correspondingly attached to the solder pads of the device-mounting region by means of a solder paste, for electrically connecting the passive devices to the substrate; an insulative material for encapsulating the passive devices and part of the substrate; a semiconductor chip having an active surface for forming a plurality of electrical circuits and bonding pads thereon, and an inactive surface directly or indirectly attached to a surface of the insulative material above the passive devices; a plurality of gold wires for electrically connecting the semiconductor chip to the substrate; an encapsulant for encapsulating the semiconductor chip and the gold wires; and a plurality of array-arranged conductive members electrically connected to a bottom surface of the substrate.
The invention is characterized in that the passive devices are vertically integrated under the semiconductor chip without occupying the surface area of the substrate so as to miniaturize the semiconductor package in profile. Moreover, prior to a wire bonding process, the passive devices are encapsulated by the insulative material, effectively allowing restrictions on positioning the bonding pads and the passive devices to be avoided, so as to remarkably improve the flexibility of substrate routability.
On the other hand, the passive devices are attached to the solder pads of the substrate through a solder paste with the use of surface-mount technology (SMT) and are hermetically encapsulated by the insulative material prior to a molding process, so that the dislocation of the passive devices caused by a high temperature and mold flow of a molding resin can be prevented from occurrence. Furthermore, as the encapsulated passive devices is free of direct contact with the semiconductor chip or the bonding wires, the occurrence of short circuit can be avoided and the quality of the packaged product is improved.
REFERENCES:
patent: 5249354 (1993-10-01), Richman et al.
patent: 5355283 (1994-10-01), Marrs et al.
patent: 5847445 (1998-12-01), Wark et al.
patent: 6022583 (2000-02-01), Falcone et al.
Chu Yude
Chuang Jui-Yu
Huang Chian Ping
Tsai Ho-Yi
Wu Chi Chuan
Corless Peter F.
Edwards & Angell LLP
Jensen Steven M.
Lee Hsien Ming
Siliconware Precision Industries Co. Ltd.
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