Semiconductor package having multi-signal bus bars

Details Semiconductor package having multi-signal bus bars Semiconductor package having multi-signal bus bars

2001-11-09

2004-04-20

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S698000, C257S713000

Reexamination Certificate

active

06724077

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention generally relates to semiconductor packages. More particularly, the invention relates to a semiconductor package having a multi-signal bus bar architecture.
2. Discussion
In the computer industry, there is a well documented trend toward faster processing speeds and enhanced functionality. While the above trend is highly desirable to the consumer, it presents significant challenges to chip designers and manufacturers. One area of particular concern is semiconductor packaging. A primary function of the typical semiconductor package is to facilitate electrical interconnection between an integrated circuit (IC) such as a computer processor encapsulated within a semiconductor die, and a printed wiring board (PWB) on which various other components are mounted. One approach is to use a substrate having a die side coupled to the IC and a socket interface, which allows the semiconductor package to be “plugged” into a mating socket such as a zero insertion force (ZIF) socket. The socket interface under such an approach has traditionally been a uniform pin architecture, wherein each pin enables a reference or input/output (I/O) signal to be transported between the substrate and the socket.
While the above approach has provided an acceptable solution under certain conditions, the trend toward faster clock speeds and increased functionality has resulted in an increased demand for current that cannot fully be met under the traditional uniform pin architecture. In response to the above-described need, certain approaches to modifying the socket interface have involved the use of a hybrid architecture, which includes both pins and bus bars. Under such an approach, pins enable I/O signals to be transported between the substrate and the socket, whereas bus bars are used for reference signals. The conventional bus bar has a first member, a second member and a dielectric “sandwiched” between the first and second members. The first and second members typically transport reference signals such as V
cc
or V
SS
to the processor, and have a relatively large planar geometry to increase power handling capacity.
It is important to note that while the above-described hybrid architecture has increased the power handling capacity of conventional semiconductor packages, certain difficulties remain. A particular concern relates to the manufacturability of the semiconductor package. For example, it has been determined that it is difficult to maintain acceptable pin alignment tolerances when the socket interface utilizes the hybrid architecture. Furthermore, conventional designs for the outer members of the bus bar prohibit the use of bus bars for I/O signals due to the large amount of area taken up by each bus bar.


REFERENCES:
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patent: 2002/0004335 (2002-01-01), Onizuka
Patent Abstracts of Japan, vol. 199, No. 8, Jun. 30, 1999, & JP 11 067985 (Hiroshima Nippon Denki KK), Mar. 9, 1999.

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