Semiconductor package having insulated metal substrate and...

Details Semiconductor package having insulated metal substrate and... Semiconductor package having insulated metal substrate and...

2009-12-18

2010-11-30

Pham, Hoai V (Department: 2892)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S112000, C257SE21499

Reexamination Certificate

active

07842545

ABSTRACT:
Provided is a semiconductor package in which an adhesion force between an insulation metal substrate and a molding member is increased by removing a solder mask layer from the insulation metal substrate and a method of fabricating the semiconductor package. The semiconductor package includes an insulation metal substrate that includes a base member, an insulating layer disposed on the base member, and conductive patterns formed on the insulating layer. Semiconductor chips are arranged on the conductive patterns. Solder mask patterns are arranged on the conductive patterns to surround the semiconductor chips. Leads are electrically connected to the conductive patterns through wires. A sealing member is arranged on an upper surface and side surfaces of the substrate to cover portions of the leads, the wires, the semiconductor chips, and the solder mask patterns.

REFERENCES:
patent: 7550322 (2009-06-01), Kimura

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