Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
2001-12-12
2003-05-20
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C438S113000, C438S123000, C438S127000, C438S613000, C257S676000
Reexamination Certificate
active
06566168
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor package and a method for manufacturing the same, and more particularly, to a chip scale package (CSP) which does not include a lead or uses a solder ball instead of a lead.
2. Description of the Related Art
Recently, electronic products such as personal computers, cellular phones and camcorders have became smaller in size and larger in processing capacity. Accordingly, a semiconductor package which is small in size, large in capacity and compliant with a fast processing speed is required. Therefore, semiconductor packages have been transformed from an insertional mounting type including a dual inline package (DIP) into a surface mounting type including a thin small out-line package (TSOP), a thin quad flat package (TQFP) and a ball grid array (BGA).
The BGA, among the surface mounting types, has attracted considerable attention since allows the size and the weight of a semiconductor package to be greatly reduced and relatively high quality and reliability to be achieved among chip scale packages.
FIGS. 1 through 3
are views illustrating the structure of a conventional BGA package using a rigid substrate.
FIG. 1
is a sectional view of the conventional BGA package using a rigid substrate.
FIG. 2
is a partially cut-away plan view of the conventional BGA package.
FIG. 3
is a bottom view of the conventional BGA package.
Referring to
FIGS. 1 through 3
, in a typical BGA package, a semiconductor package is assembled using a rigid substrate
10
instead of a lead frame. In other words, a semiconductor chip
6
is bonded to the surface of the rigid substrate
10
with a die-bonding epoxy
5
. A bond finger
2
formed on the rigid substrate
10
is connected to a bond pad of the semiconductor chip
6
using a gold wire
4
. After completing wire bonding, the rigid substrate
10
and the semiconductor chip
6
are molded with an epoxy mold compound (EMC) which is a sealing resin
7
. Thereafter, a solder ball
13
, an external connecting terminal, is attached to a solder ball pad, a circuit pattern, which connects the top to the bottom in the rigid substrate
10
through a via-hole
9
formed in the rigid substrate
10
.
In the drawings, reference numeral
1
denotes a solder mask formed on the front surface of the rigid substrate
10
, reference numeral
3
denotes a front conductive land, reference numeral
11
denotes a rear solder mask, and reference numeral
12
denotes an insulation substrate. In
FIG. 3
, reference numeral
6
′ denotes a position to which the semiconductor chip
6
is bonded.
In a conventional BGA package using a rigid substrate, it is essential to form the via-holes
9
and the front and rear conductive lands for attachment of external connecting terminals. Since many intermediate connecting terminals are formed within a semiconductor package in such arrangement, the length of interconnection between a bond pad in a semiconductor chip and an external connecting terminal is long, thereby deteriorating the electrical conductivity of the semiconductor package.
Moreover, the front and rear solder masks
1
and
11
, which are used for insulation and protection of the conductive lands on the front and rear surfaces of the rigid substrate
10
, are delaminated after a semiconductor package is completely assembled, thereby decreasing the reliability of the semiconductor package.
The rigid substrate
10
necessarily includes an insulation substrate
12
. The insulation substrate
12
remains within a semiconductor package after the semiconductor package is completely assembled. Accordingly, the thickness of the insulation substrate
12
within the semiconductor package restrains decrease in the thickness of a BGA package.
Besides, many other parts are packaged with a rigid substrate within a semiconductor package. Defects caused by differences between thermal expansive coefficients of many parts deteriorate the reliability of the semiconductor package.
FIGS. 4 through 6
are views illustrating the structure of a conventional BGA package using a substrate where conductive lands are formed on a tape film.
FIG. 4
is a sectional view illustrating the conventional BGA package using a substrate where conductive lands are formed on a tape film.
FIG. 5
is a partially cut-away plan view of FIG.
4
.
FIG. 6
is a bottom view of FIG.
4
.
Referring to
FIGS. 4 through 6
, a tape film
23
on which conductive lands are formed is used instead of a rigid substrate. Conductive lands are formed on the tape film
23
which is an insulation substrate formed of a polyimide resin by performing a punching or etching process to form holes. The tape film
23
having the conductive lands is used as a base substrate in assembling a semiconductor package.
Accordingly, a front solder mask
21
and a rear solder mask
28
are formed on the tape film
23
for insulation and protection of the conductive lands. The tape film
23
including the front and rear solder masks
21
and
28
remains as part of the semiconductor package after completing the assembly of the semiconductor package.
In the drawings, reference numeral
22
denotes a bond finger, reference numeral
24
denotes gold wire, reference numeral
25
denotes a die-bonding epoxy, reference numeral
26
denotes a semiconductor chip, reference numeral
27
denotes a sealing resin, reference numeral
29
denotes a solder ball pad, and reference numeral
30
denotes a solder ball. In
FIG. 6
, reference numeral
26
′ denotes a position to which the semiconductor chip
26
is bonded.
However, a conventional BGA package using a tape film in which conductive lands are formed requires an additional process such as punching or etching for forming a hole connecting the solder pad
29
to the bond finger
22
. Moreover, the tape film
23
that remains within a semiconductor package after completion of assembly of the semiconductor package hinders in decreasing the thickness of the semiconductor package. Also, various defects are caused by differences between thermal expansive coefficients of the tape film
23
and other parts packaged within the semiconductor package, thereby deteriorating the reliability of the semiconductor package.
FIGS. 7 through 9
are views illustrating the structure of a conventional quad flat no-lead (QFN) package.
FIG. 7
is a sectional view of the conventional QFN package.
FIG. 8
is a partially cut-away plan view of FIG.
7
.
FIG. 9
is a bottom view of FIG.
7
.
Referring to
FIGS. 7 through 9
, a semiconductor chip
44
is bonded to a chip pad
50
serving as a heat sink, and to a lead frame
49
including only an internal lead
41
, with a die-bonding epoxy
43
, and wire bonding is performed using gold wire
42
. Thereafter, the lead frame
49
and the semiconductor chip
44
are molded with a sealing resin
45
which is an EMC.
In the drawings, reference numeral
51
denotes a region where ground bonding is performed, and reference numeral
52
denotes a region where bonding of a usual input/output terminal is performed. Reference numeral
53
denotes an internal lead for an input/output terminal of a semiconductor package, and reference numeral
54
denotes an internal lead for a ground terminal.
However, for a conventional QFN package, the lead frame
49
should be formed of copper or an alloy of copper, and this lead frame
49
remains as the part of the semiconductor package after completion of assembly of the semiconductor package, thereby hindering in decreasing the thickness of the semiconductor package. Moreover, during a singulation process for taking off individual semiconductor packages from a strip of semiconductor packages, it is very difficult to take off a semiconductor package including the lead frame
49
, thereby causing many defects. Besides, many internal leads
53
for input/output terminals restrict the space where they are arranged in a semiconductor package.
SUMMARY OF THE INVENTION
To solve the above problems, it is a first object of the present invention to provi
Huynh Andy
KOSTAT Semiconductor Co., Inc.
Rothwell Figg Ernst & Manbeck
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