Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
2000-01-28
2001-09-11
Le, Vu A. (Department: 2824)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C438S612000, C438S106000, C438S108000
Reexamination Certificate
active
06287895
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a semiconductor package, and more particularly to, a semiconductor package that is connected with a printed wiring board using a ball grid array (BGA).
BACKGROUND OF THE INVENTION
In the case that a chip size package (CSP) as a semiconductor package is mounted on a printed wiring board and the package main body is connected with the printed wiring board only through solder balls, if a stress in the vertical direction is applied to the ends of the chip size package, then a solder connection opposed to part to which the stress is applied is broken. To avoid this breaking, conventionally used is a method that dummy members as a spacer are disposed at the ends of the package, thereby keeping the spacing between the package main body and the printed wiring board constant, thus protecting the solder connection parts of the ball grid array.
FIGS. 1A and 1B
are a front view and top view, respectively, showing the shape of chip size package after mounting the solder balls and dummy member by the conventional method for making semiconductor package. Here, shown is a chip size package that is provided with one semiconductor chip (not shown) diced from a semiconductor wafer. There are provided protective dummy members
2
(protective parts) that are of round resinous or metallic material with a predetermined height at the corners on the surface of a package main-body board
1
that has a size nearly equal to that of the semiconductor chip. On a region
4
except these parts, there are mounted multiple solder balls
3
, which compose a ball grid array (BGA), at predetermined intervals. The protective dummy member
2
is a protrusion provided to protect the ball grid array during fabrication of the package. The diameter of the protective dummy members
2
is set to be larger than that of the solder balls
3
, and the solder balls
3
are disposed avoiding the regions of the protective dummy members
2
. Therefore, array area
4
as the mounting region of the solder balls
3
is approximately hexagonal.
FIG. 2
is a flow chart showing the conventional method for making a semiconductor package. First, the package main-body board
1
is prepared (step
201
). Then, a semiconductor chip (not shown) diced from a semiconductor wafer is mounted on the package main-body board
1
(step
202
). Then, after wire-bonding lands on the semiconductor chip to a wiring pattern (or lands) on the package main-body board
1
(step
203
), the surface subject to the bonding is sealed with resin mold (step
204
). Further, as shown in
FIG. 1A
, the solder balls
3
are mounted on corresponding lands on the surface of the package main-body board
1
that is not subject to the resin molding. Then, the protective dummy members
2
are mounted using a mold tool.
As described above, in the conventional method, the molding and sealing, the mounting of solder balls, and the mounting of protective dummy members are conducted individually to each semiconductor chip.
Thus, in the conventional method for making a semiconductor package, there is a problem that the process is difficult to simplify since the molding and sealing, the mounting of solder balls, and the mounting of protective dummy members are conducted individually to each package main-body board. Therefore, it is difficult to reduce the manufacturing cost by the mass production.
Also, the protective dummy members are difficult to position at the ends of package with a high degree of accuracy. They have to be positioned a given distance (&agr; in FIG.
1
B), as a margin, apart from the ends of package. Therefore, when a stress in the vertical direction is applied to the ends of package after fabrication, it will exhibit a lowered tolerance.
In recent years, the lump transfer method that a large number of semiconductor chips can be molded in the lump has attracted attention. However, in a semiconductor device that has the structure of chip size package or ball grid array, it is difficult to attach the dummy members efficiently. Therefore, it becomes an obstacle to the practical use of the lump transfer method.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the invention to provide a method for making a semiconductor package that the protective dummy members can be disposed precisely and efficiently.
It is a further object of the invention to provide a semiconductor package that a tolerance against a stress in the vertical direction applied to the ends of package after fabrication can be enhanced.
According to the invention, a semiconductor package, comprises:
a chip-sized wiring board that has a predetermined wiring pattern;
a semiconductor chip that is mounted on the wiring board and is electrically connected to the wiring pattern;
sealing resin that seals at least the connection part of the wiring board and the semiconductor chip;
an array of solder balls for external circuit connection that are connected through an opening in the sealing resin to a land of the wiring pattern; and
a protective member that is disposed along at least two sides of the surface where the array of solder balls are provided.
In this composition, the protective members with a predetermined length are disposed along at least two sides of the surface where the array of solder balls are provided. The protective members function as a guide to maintain uniform the offset spacing between the wiring board and the package main-body board when mounting the wiring board on the package main-body board through the solder balls. Therefore, in the re-flowing the solder balls, the spacing between the wiring board and the package main-body board can be uniform at every point even when there occurs a deviation in melting among the solder balls. Thus, the cost reduction, and the mass production of semiconductor package can be advanced. Furthermore, the mounting space of solder balls can be enlarged.
According to another aspect of the invention, a method for making a semiconductor package, comprising the steps of:
mounting a plurality of semiconductor chips on a board with a predetermined dimensions that has a plurality of common wiring patterns;
electrically connecting the semiconductor chips and the corresponding wiring patterns of the board;
resin-sealing the surface of the board that incurs the electrical connection;
mounting a plurality of solder balls on the surface of the board that no semiconductor chip is mounted to form a ball grid array;
mounting a protective member with a predetermined length for protecting the ball grid array on a dicing line at both sides of the ball grid array; and
dicing the board along the dicing line to divide the protective member nearly equally in the direction of the dicing line.
In this method, a plurality of semiconductor chips are disposed on one package main-body board, then mounting the solder balls and protective members in the lump on to the plurality of semiconductor chips, then dicing it to divide into a plurality of chip size packages. Thus, the simplification of fabrication process for chip size package, the cost reduction and the mass production of chip size package can be advanced.
According to another aspect of the invention, a method for making a semiconductor package, comprises the steps of:
forming ball grid arrays of solder balls on a plurality of semiconductor chips fabricated on a semiconductor wafer after sealing with resin;
mounting a protective member with a predetermined length for protecting the ball grid arrays to locate on the borderline to section two of the ball grid arrays and on both sides of two of the ball grid arrays; and
dicing the semiconductor wafer to divide the protective member nearly equally in the direction of a dicing line.
In this method, at the stage of a semiconductor wafer, the solder balls and dummy members for each of multiple semiconductor devices are mounted, then dicing it to divide into devices. Thus, the simplification of fabrication process for semiconductor device, the coat reduction and the mass production of semiconductor device can be advanced.
Le Vu A.
McGinn & Gibb PLLC
NEC Corporation
Pyonin Adam
LandOfFree
Semiconductor package having enhanced ball grid array... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor package having enhanced ball grid array..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor package having enhanced ball grid array... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2477171