Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material
Reexamination Certificate
1999-10-12
2003-04-22
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Insulating material
C257S707000, C257S712000, C257S713000, C257S796000, C257S787000, C257S704000
Reexamination Certificate
active
06552428
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor packages, and more particularly, to a ball grid array (BGA) semiconductor package having a heat spreader for effectively performing heat dissipation.
DESCRIPTION OF THE PRIOR ART
With rapid advances and unceasing improvements in the electric technology, electronic products such as cellular phone, notebook, and PDA need to be miniaturized in both weight and size without sacrificing functions. To fulfil the tendency for miniaturization of electronic products, the integrated circuit technology adopted to integrate and increase the density of electric circuit and electronic components on a semiconductor chip plays an important role, and so does the IC packaging technology.
Purposes of packaging or encapsulating a semiconductor chip are to protect the semiconductor chip from being affected by outer contaminants such as moisture and dust, to provide an electrical connection between the semiconductor chip and a printed circuit board (PCB), and to provide structural support for preventing the semiconductor chip from being deformed or damaged. A conventional semiconductor package having a leadframe for mounting a semiconductor chip, such as Quad Flat Package (QFP) or Thin Quad Flat Package (TQFP) has a limitation to increase the number of the I/O pins and to decrease the pitch between any two adjacent I/O pins. As a result, Ball Grid Array (BGA) type semiconductor packages are developed to solve the problems existing in conventional leadframe type semiconductor packages. The BGA semiconductor package typically has an array of solder balls attached to the substrate for bearing a semiconductor chip. As the solder balls are allowed to be disposed under the semiconductor chip, the BGA semiconductor package has an optimized pin count.
For the BGA semiconductor package, heat generated from a semiconductor chip in operation is dissipated to the outside of the package via the route comprised of the semiconductor chip, silver paste, conductive traces on a top surface of a substrate, the substrate, conductive traces on a bottom surface of the substrate, and solder balls. However, the thermal conductive path for a BGA semiconductor package is so long that the heat generated by the semiconductor chip can not be effectively and efficiently dissipated out of the package body via the aforementioned heat dissipating path, while the density of semiconductor components and electric circuit on the semiconductor chip is considerably increased. Thus, a BGA semiconductor package having a heat spreader for improving thermal conductivity has been disclosed in U.S. Pat. No. 5,736,785. As shown in
FIGS. 10 and 11
, the semiconductor package of U.S. Pat. No. 5,736,785 has a heat spreader
116
, which sits on the top surface of the substrate
104
to which the die
102
is adhered, for effectively dissipating heat. There are first supporters
116
f
at corners of the square-shaped heat spreader
116
for preventing the die
102
from being moved and damaged while the heat spreader
116
is disposed in the package body
112
. A shallow dish-like recessed portion
116
a
protrudes from the central portion of bottom surface of the heat spreader
116
to contact a top surface of the die
102
for effectively dissipating heat generated by the die
102
to the outside of a package body through the heat spreader
116
. Meanwhile, four hemispherical downward projections
116
c
are provided on corners of the heat spreader
116
. And the downset of the hemispherical downward projections
116
c
is adapted to be deeper than that of the shallow disk-like recessed portion
116
a
so that when mounted on the top surface of the substrate
104
, the heat spreader
116
is supported by the hemispherical downward projections
116
c
without causing pressure to the die
102
. There are four openings
116
b
formed on the heat spreader
116
for allowing the packaging resin to flow into space under the heat spreader
116
during molding process.
Such semiconductor package can effectively increase the efficiency of heat dissipation by making the heat spreader
116
in contact with the die
102
. However, for packaging the die
12
and the heat spreader
116
with packaging resin, the packaging process needs to take extra steps to adhere the bottom surface of the shallow disk-like recessed portion
116
a
of the heat spreader
116
to the die
102
, when compared with conventional packaging operation for BGA semiconductor packages. The packaging process for such semiconductor package comprises the following steps of; (a) attaching the die
102
to the top surface of the substrate
104
, and making electrical connection from the die
102
to the substrate
104
by gold wires
108
; (b) preparing a fixture for the substrate
104
to allow the die
102
to be received in an opening of the fixture; (c) daubing the die
102
, a portion o fate substrate
104
, and gold wires
108
with epoxy resin through the opening of the fixture; (d) setting the heat spreader
116
on the top surface of the chip
102
via the opening of the fixture, and adjusting a location of the heat spreader
116
by using the fixture to downwardly press the heat spreader
116
for letting the top surface of the heavy spreader
116
to be covered with the epoxy resin, and to attach the heat spreader
116
to the top surface of the chip
102
via the epoxy resin; (e) removing the fixture, and curing the epoxy resin; and (f) proceeding the molding process.
However, the aforementioned process, which takes time longer than conventional processes, has drawbacks as follows: (a) A fixture is needed to adjust the location of the heat spreader on the top surface of the chip
102
prior to adhering the heat spreader
116
to the chip
102
. However, there is required a permissible gap between the edge of the heat spreader
116
and the fixture to allow the heat spreader
116
be clipped and adopted inside the fixture, so that the location of the heat spreader
116
, corresponding to the chip
102
, is not precisely set over the semiconductor chip
102
, and then, an off-center phenomena resulted from the misalignment between the heat spreader
116
and the chip
102
would affect the outlook of the semiconductor package. (b) Compared with conventional process, although each step, from aforesaid step (b) to (e), of the molding process of U.S. Pat. No. 5,736,785 can be accomplished in the same work area, however, extra steps which are step (b) to step (c) are still needed for the molding process, and thus, the molding process is more complicated than convention one and the production cost would increase. (c) Due to different expansion coefficient of the heat spreader
116
and the chip
102
, after the heat spreader
116
has been adhered to the top surface of the chip
102
and the molding process has been accomplished, a de-lamination phenomena resulted from a interface between the heat spreader
116
and the chip
102
would degrade qualities of products. (d) In addition, the heat spreader
116
should be adhered to the chip
102
and the chip
102
is sensitive to pressures inside the encapsulant so that when the upper and lower mold half are combined together for introducing the epoxy resin into cavities of the two mold halves, the pressure resulted from the resin flow inside cavities will exert to the chip
102
via the heat spreader
116
, causing the chip
102
to be cracked; meanwhile, a thermal stress caused by high temperature effect during the molding process is still remained inside the heat spreader
116
, and that would crack the chip
102
, while the resin is cured. (e) Further, there are a dish-like recessed portion
116
a
of the central region of the heat spreader
116
, and four hemispherical downward projections
116
c
on four corners, so that during the molding process, the epoxy resin which flows into a cavity between the upper mold half and the chip
102
would be retarded by the dish-like recessed portion
116
a
and the hemispherical downward projections
116
c
, and then, a turbul
Chiang Kevin
Huang Chien Ping
Lai Jenq-Yuan
Liu Vicky
Tang Tom
Corless Peter F.
Crane Sara
Edwards & Angell LLP
Jensen Steven M.
Parekh Nitin
LandOfFree
Semiconductor package having an exposed heat spreader does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor package having an exposed heat spreader, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor package having an exposed heat spreader will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3093630