Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2011-03-22
2011-03-22
Huynh, Andy (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S737000, C257S778000, C257S786000, C257SE23010, C257SE23021
Reexamination Certificate
active
07911065
ABSTRACT:
A semiconductor package having a stacked wafer level structure includes a base substrate; a semiconductor chip; a redistribution pattern; and a second insulation layer pattern. The base substrate having a chip region and a peripheral region disposed at the periphery of the chip region. The semiconductor chip is disposed over the chip region and has a bonding pad. The first insulation layer pattern covers the chip region and the peripheral region and exposes the bonding pad. The redistribution pattern is disposed over the first insulation layer pattern and extends from the bonding pad to the peripheral region. The second insulation layer pattern is disposed over the first insulation layer pattern and opening some portion of the redistribution pattern disposed in the peripheral region.
REFERENCES:
patent: 7045899 (2006-05-01), Yamane et al.
patent: 2006/0125072 (2006-06-01), Mihara
patent: 2006/0231958 (2006-10-01), Yang
patent: 2005-353837 (2005-12-01), None
Huynh Andy
Hynix / Semiconductor Inc.
Ladas & Parry LLP
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