Semiconductor package having a bridged plate interconnection

Details Semiconductor package having a bridged plate interconnection Semiconductor package having a bridged plate interconnection

2007-09-28

2009-11-24

Estrada, Michelle (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

C257S341000, C257S401000, C257S522000, C257S579000, C257S587000, C257S692000, C257S735000, C257SE21451, C257SE29318

Reexamination Certificate

active

07622796

ABSTRACT:
A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, and a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of metalized source contacts. A bridged source plate interconnection has a bridge portion, valley portions disposed on either side of the bridge portion, plane portions disposed on either side of the valley portions and the bridge portion, and a connection portion depending from one of the plane portions, the bridged source plate interconnection connecting the source lead with the plurality of metalized source contacts. The bridge portion is disposed in a plane above the plane of the valley portions while the plane portions are disposed in a plane intermediate the plane of the bridge portion and the plane of the valley portions.

REFERENCES:
patent: 3735017 (1973-05-01), Manning
patent: 3737738 (1973-06-01), Koenig
patent: 3842189 (1974-10-01), Southgate
patent: 4083063 (1978-04-01), Yu
patent: 4104786 (1978-08-01), Boah et al.
patent: 4418470 (1983-12-01), Naster et al.
patent: 4996582 (1991-02-01), Nagahama
patent: 5480841 (1996-01-01), Bickford et al.
patent: 5753942 (1998-05-01), Seok
patent: 5864169 (1999-01-01), Shimura et al.
patent: 6040626 (2000-03-01), Cheah et al.
patent: 6136702 (2000-10-01), Chandross et al.
patent: 6249041 (2001-06-01), Kasem et al.
patent: 6287126 (2001-09-01), Berger et al.
patent: 6292140 (2001-09-01), Osterman
patent: 6294787 (2001-09-01), Schieferdecker et al.
patent: 6316827 (2001-11-01), Asano et al.
patent: 6548882 (2003-04-01), Zwicknagl et al.
patent: 6724067 (2004-04-01), Bayraktaroglu
patent: 6849930 (2005-02-01), Nakajima et al.
patent: 6881074 (2005-04-01), McLenaghan
patent: 7230322 (2007-06-01), Funato et al.
patent: 7253507 (2007-08-01), Kouzuki et al.
patent: 2001/0045593 (2001-11-01), De Leeuw et al.
patent: 2003/0038341 (2003-02-01), Bayraktaroglu
patent: 2004/0124435 (2004-07-01), D'Evelyn et al.
patent: 2005/0127532 (2005-06-01), Luo
patent: 2005/0194638 (2005-09-01), Kouzuki et al.
patent: 2006/0012055 (2006-01-01), Foong et al.
patent: 2006/0157804 (2006-07-01), Ueda
patent: 2006/0205161 (2006-09-01), Das et al.
patent: 2007/0057368 (2007-03-01), Ho
patent: 2007/0090913 (2007-04-01), Kim
patent: 2007/0114352 (2007-05-01), Cruz et al.
patent: 2007/0235341 (2007-10-01), Mizohata et al.
patent: 2007/0290336 (2007-12-01), Sun et al.
patent: 2008/0054438 (2008-03-01), Germain et al.
U.S. Appl. No. 11/799,467, filed Apr. 30, 20078, entitled Semiconductor Package Having Dimpled Plate Interconnections, and having Ming Sun, Lei Shi and Kai Liu listed as inventors.
U.S. Appl. No. 12/321,761, filed Jan. 23, 2009, entitled Semiconductor package having a bridge plate connection, and having Ming Sun, Lei Shi and Kai Liu listed as inventors.
U.S. Appl. No. 12/474,107, filed May 28, 2009, entitled Semiconductor Package Having a Bridged Plate Interconnection, and having Lei Shi, Ming Sun and Kai Liu listed as inventors.
International Search Report mailed Dec. 29, 2008 for International Patent Application No. PCT/US08/11202.
Written Opinion mailed Dec. 29, 2008 for International Patent Application No. PCT/US08/11202.
International Search Report mailed Sep. 25, 2007 for International Patent Application No. PCT/US2006/035641.
Written Opinion mailed Sep. 25, 2007 for International Patent Application No. PCT/US2006/03564.
International Preliminary Report on Patentability issued Mar. 18, 2008 for International Patent Application No. PCT/US2006/03564.
Office Action Mailed Sep. 26, 2008 for U.S. Appl. No. 11/799,467, filed Apr. 30, 2007.
Non-final Rejection Mailed Feb. 27, 2007 for U.S. Appl. No. 11/226,913, filed Sep. 13, 2005.
Non-final Rejection Mailed Oct. 5, 2004 for U.S. Appl. No. 10/732,181, filed Dec. 9, 2003.

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