Semiconductor package form within an encapsulation

Details Semiconductor package form within an encapsulation Semiconductor package form within an encapsulation

2005-11-23

2010-06-01

Gurley, Lynne A (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S734000, C257S737000, C257SE23174

Reexamination Certificate

active

07728437

ABSTRACT:
Provided are a semiconductor package which is small in size but includes a large number of terminals disposed at intervals equal to or greater than a minimum pitch, and a method of fabricating the semiconductor package. The semiconductor package includes a semiconductor chip having a bottom surface on which a plurality of bumps are formed, redistribution layer patterns formed under the semiconductor chip and each including a first part electrically connected to at least one of the bumps and a second part electrically connected to the first part, an encapsulation layer surrounding at least a top surface of the semiconductor chip, and a patterned insulating layer formed below the redistribution layer patterns and exposing at least parts of the second parts of the redistribution layer patterns.

REFERENCES:
patent: 4940181 (1990-07-01), Juskey, Jr. et al.
patent: 5092033 (1992-03-01), Nishiguchi et al.
patent: 5501004 (1996-03-01), Onitsuka
patent: 5859924 (1999-01-01), Liu et al.
patent: 5877549 (1999-03-01), Kim
patent: 5986334 (1999-11-01), Lee
patent: 6001671 (1999-12-01), Fjelstad
patent: 6013948 (2000-01-01), Akram et al.
patent: 6093584 (2000-07-01), Fjelstad
patent: 6135522 (2000-10-01), Su et al.
patent: 6190509 (2001-02-01), Haba
patent: 6190717 (2001-02-01), Benham
patent: 6191477 (2001-02-01), Hashemi
patent: 6239482 (2001-05-01), Fillion et al.
patent: 6252301 (2001-06-01), Gilleo et al.
patent: 6306685 (2001-10-01), Liu et al.
patent: 6336990 (2002-01-01), Tanaka et al.
patent: 6368896 (2002-04-01), Farnworth et al.
patent: 6392305 (2002-05-01), Huang et al.
patent: 6396557 (2002-05-01), Tajima
patent: 6407508 (2002-06-01), Kawada et al.
patent: 6426554 (2002-07-01), Egawa
patent: 6441498 (2002-08-01), Song
patent: 6468830 (2002-10-01), Carson
patent: 6476503 (2002-11-01), Imamura et al.
patent: 6518091 (2003-02-01), Haba
patent: 6518097 (2003-02-01), Ym et al.
patent: 6528344 (2003-03-01), Kang
patent: 6528893 (2003-03-01), Jung et al.
patent: 6541848 (2003-04-01), Kawahara et al.
patent: 6555917 (2003-04-01), Heo
patent: 6566748 (2003-05-01), Shimizu et al.
patent: 6582979 (2003-06-01), Coccioli et al.
patent: 6611052 (2003-08-01), Poo et al.
patent: 6611055 (2003-08-01), Hashemi
patent: 6621286 (2003-09-01), Takada et al.
patent: 6751781 (2004-06-01), Lin et al.
patent: 6756666 (2004-06-01), Hosomi
patent: 6949142 (2005-09-01), Charpin
patent: 2004/0032013 (2004-02-01), Cobbley et al.
patent: 2004/0195701 (2004-10-01), Attarwala
patent: 2006/0261364 (2006-11-01), Suehiro et al.
H. Theuss, K. Pressel, S. Paulus, T. Kilger, J. Dangelmaier, R. Lehner, B. Eisener, H. Kiendl, J. Schischka, A. Graff, M. Petzold, “A Highly Reliable Flip Chip Solution based on Electroplated AuSn Bumps in a Leadless Package”, 0-7803-8906, Sep. 2005 © 2005 IEEE; pp. 272 through 279.

Affiliated with

Also associated with

Rating

Semiconductor package form within an encapsulation does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor package form within an encapsulation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor package form within an encapsulation will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4204102