Semiconductor package for memory chips

Details Semiconductor package for memory chips Semiconductor package for memory chips

2005-11-08

2005-11-08

Cao, Phat X. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

For plural devices

C257S685000, C257S686000

Reexamination Certificate

active

06963135

ABSTRACT:
A semiconductor package includes two substrates each having a plurality of electrical connection pads, at least one chip mounted on each of the substrates, an encapsulation body formed on each of the substrates for encapsulating the chip, and an cover for receiving the substrates and the chips therein. The chip is electrically connected to the electrical connection pads. The electrical connection pads are exposed from the cover and located on the same surface or oppositely arranged. The substrates and the cover each substantially has a rectangular shape, with a longer side of each of the substrates being vertical to a longer side of the cover. The semiconductor package is incorporated with multiple chips to enhance the performance and memory capacity thereof, and the substrates are smaller than those in the prior art and thus are more cost-effective to fabricate.

REFERENCES:
patent: 4264917 (1981-04-01), Ugon
patent: 5677524 (1997-10-01), Haghiri-Tehrani
patent: 5866953 (1999-02-01), Akram et al.
patent: 6040622 (2000-03-01), Wallace
patent: 6570249 (2003-05-01), Liao et al.
patent: 62-239554 (1987-10-01), None

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