Semiconductor package for chip with testing contact pad...

Details Semiconductor package for chip with testing contact pad... Semiconductor package for chip with testing contact pad...

2001-05-31

2003-11-04

Nguyen, Vinh P. (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S1540PB

Reexamination Certificate

active

06642735

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89126422 filed on Dec. 12, 2000.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor package for chip with testing contact pad. More particularly, the invention relates to a leadframe semiconductor package for chip with testing contact pad.
2. Description of the Related Art
As the era of information technology progresses, the transmission and processing of information and documents are increasingly carried out via more sophisticated and miniaturized electronic products.
As the semiconductor manufacturing enters the era of 0.18 microns, the testing of the chip is necessary to ensure the quality of the chip manufacturing process. The chip thus is usually provided with a plurality of testing contact pads thereon. The testing of the chip via the testing contact pads allows for the detection and removal of the deficient chips that are not unnecessarily packaged.
More particularly with respect to memory devices such as DRAM, the packaging structures principally used are the small-outline J-lead (SOJ) packaging structure and the thin-small outline packaging structure (TSOP). Within both above packaging structures, the leadframe arranged on the generally square-shaped chip is usually constructed with an arrangement of the leads proximate to two sides of the chip while a plurality of flow-conducting plate is located respectively on the two other sides of the chip. The flow-conducting plates maintain the uniformity of the flow of the molding compound while it is injected during the encapsulation of the chip. There are two principal types of lead arrangement in the leadframe used for the small outline J-lead (SOJ) packaging structure or the thin-small outline packaging structure (TSOP), which are the lead on chip (LOC) and the chip on lead (COL) arrangements. The lead on chip (LOC) arrangement package is principally used as DRAM packaging structure, the advantages thereof are a fast signal transmission, a good heat dissipation and a small size of the packaging structure.
Referring to
FIG. 1
, a top view schematically shows a conventional lead-on-chip (LOC) packaging structure. The conventional lead-on-chip (LOC) package
100
comprises a chip
110
, a plurality of leads
130
and a molding compound
170
. The chip
110
has an active surface
112
provided with a plurality of functional contact pads
114
and a plurality of testing contact pads
116
thereon. The testing contact pads
116
are used to test the chip
110
before it is packaged. During the mass production, the testing contact pads
116
are not connected to any leads
130
. The leads
130
are respectively bonded onto two sides of the active surface
112
of the chip
110
, while a pair of flow-conducting plates
150
with a plurality of flow-conducting holes
152
therein are located on the two other sides of the chip
110
. The flow-conducting holes
152
uniformize the flow of the molding compound when it is injected during molding such that an excessive differential pressure between the upper and lower side of the flow conducting plates
150
can be prevented. A plurality of wires
160
connect respectively the functional contact pads
114
and the leads
130
, and a molding compound
170
encapsulates the chip
110
, the leads
130
, the wires
160
and the flow conducting plates
150
.
The above-described conventional package
100
has at least the following drawback. Because the testing contact pads
116
are encapsulated inside the molding compound
170
and are not accessible, if a deficiency of the chip appears after encapsulating, it is necessary to break the molding compound
170
and connect the testing contact pads
116
to an external testing circuit (not shown) to detect the cause of the deficiency. The decaping of the package thus performed principally consists in etching the molding compound. Such an operation is cumbersome and complicated to carry out, which is contrary to the goal of an improved productivity.
SUMMARY OF THE INVENTION
A major aspect of the present invention is to provide a semiconductor package for chip with testing contact pad in which if a deficiency of the chip appears after the chip is encapsulated, the package can be tested to detect the cause of the deficiency without breaking the molding compound.
To accomplish at least the foregoing objectives, the present invention, according to a preferred embodiment, provides a semiconductor package for chip with testing contact pad that comprises the following elements. A chip has an active surface provided with a plurality of functional contact pads and at least a testing contact pad thereon. A plurality of leads are bonded onto the active surface of the chip and respectively connected to the functional contact pads through a plurality of functional wires, each of the leads respectively extending outwardly into an outer lead. At least a flow-conducting plate has a plurality of flow-conducting holes therein and is connected to the testing contact pads through at least a testing wire, the flow-conducting plate being proximate to the testing contact pads of the chip. A molding compound encapsulates the chip, the leads, the flow-conducting plate, the functional wires and the testing wires. Specifically, the flow-conducting plates respectively extend outwardly into an outer connection member that is exposed to the outside of the package and can electrically connect to an external testing circuit.
To accomplish at least the above objectives, the present invention, according to another preferred embodiment, provides a semiconductor package for chip with testing contact pad that comprises the following elements. A chip has an active surface and a corresponding back surface, wherein the active surface of the chip has a plurality of functional contact pads and at least a testing contact pad. A die pad is bonded to the back surface of the chip. A plurality of leads are connected to the functional contact pads through a plurality of functional wires, wherein the leads extend outwardly into a plurality of outer leads. At least a flow-conducting plate has a plurality of flow conducting holes therein and is connected to the testing contact pads through at least a testing wire, wherein the flow-conducting plate is proximate to the testing contact pads of the chip. A molding compound encapsulates the chip, the die pad, the leads, the flow-conducting plates, the functional wires and the testing wire. Specifically, the flow-conducting plates respectively extend outwardly into an outer connection member that is exposed to the outside of the package and can electrically connect to an external testing circuit.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5428247 (1995-06-01), Sohn et al.
patent: 5677566 (1997-10-01), King et al.

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