Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reissue Patent
1998-09-14
2001-10-16
Gaffin, Jeffrey (Department: 2841)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S118000, C438S123000, C438S126000, C438S127000, C438S977000, C029S827000, C029S841000, C029S856000, C264S272170, C257S691000, C257S693000, C257S696000, C257S787000, C174S050510, C361S773000, C361S775000, C361S783000, C361S813000
Reissue Patent
active
RE037413
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor package, and more particularly to a semiconductor package suitable for packaging a center pad layout-shaped memory chip wherein paddles of a lead frame are removed and outer leads of a lead frame are not protruded from the package but only exposed to a lower surface of molding resin of a semiconductor package.
2. Description of the Prior Art
Generally, semiconductor packages may be mainly classified into a semiconductor of SOP (small outline package) type and a semiconductor of SOJ (small outline J-lead) type.
In this case, the semiconductor packages are manufactured in accordance to following procedures. A semiconductor chip is attached on paddles of a lead frame and then wire bonding is carried out between inner leads of the lead frame and pads on the semiconductor chip. The wire bonded semiconductor and lead frame are molded by molding resin. Thereafter, the resulting product is subjected to deflash, trimming and forming procedures so that outer leads of the lead frame are protruded from the molded resin and then bent into predetermined shape respectively.
Referring to
FIGS. 2 and 3
, there are shown a front section and a bottom of a semiconductor package of LOC (lead on chip) type. In the semiconductor package shown in
FIGS. 2 and 3
, a semiconductor chip
3
is formed with a plurality of bond pads
3
a at central portion thereof. Inner leads
4
a of a lead frame
4
without paddles are attached on a surface of the semiconductor chip
3
at both sides of the bond pads
3
a by means of insulation tapes
6
. The inner leads
4
a are electrically connected to the bond pads
3
a of the semiconductor chip
3
by means of metal wires
7
, respectively. Also, power supplying pads of the bond pads
3
a are electrically connected to bus bars
5
by metal wires
7
, respectively. Thereafter, the resulting semiconductor chip
3
and the inner leads
4
a of the lead frame
4
are molded by molding resin
1
.
The above-mentioned prior semiconductor packages are manufactured in such a manner that a semiconductor chip aggregate is subjected to a sawing step for dividing the semiconductor chip aggregate into separate semiconductor chips
3
and the semiconductor chip
3
is subjected to a die bonding step for attaching the separated semiconductor chip
3
to a lead frame
4
, a wire bonding step for electrically connecting bond pads
3
a of the semiconductor chip
3
to inner leads
4
a of the lead frame
4
respectively, a molding step for enveloping the wire bonded semiconductor chip
3
and lead frame
4
, a deflashing step, a solder plating step, a trimming step for cutting dampers of the lead frame
4
, a forming step for bending outer leads into a certain shape, and a marking step.
The semiconductor package prepared as described above have outer leads protruded from the mold resin. The outer leads are formed into a certain shape and then mounted on a printed circuit board.
However, the prior semiconductor packages have various disadvantages as follows. The prior semiconductor packages occupy large space due to the outer leads protruded from mold resins when the semiconductor packages are mounted on printed circuit boards.
Since the semiconductor packages have outer mechanical shock when their forming procedure, fine gaps may occur in contact areas between outer leads protruded from package bodies and mold resins, thereby causing humidity resistant property to be deteriorated due to the gaps.
Also, since the semiconductor packages require a trimming step and a forming step after a molding procedure, manufacturing process of the packages becomes complicated so that their manufacturing cost and poor products occurring rate are increased.
In addition, in case of the LOC type of semiconductor packages using lead frames without paddles, electrical property is decreased because of their long length between inner leads and outer leads.
Furthermore, so-called “good rate” which is a rate of good products in products identified as poor packages is increased because of poor lead contacts in testing of finished products.
SUMMARY OF THE INVENTION
Therefore, the present invention is made in view of the above-described prior art problems and an object of the invention is to provide a semiconductor package which is designed to occupy small space required to be mounted on a printed circuit board and to reduce manufacturing cost by omitting manufacturing procedures next to a molding procedure.
Another object of the invention is to provide a semiconductor package which has improved lead conductance and thus electrical property by reducing length between its inner leads and outer leads.
In accordance with the present invention, these object can be accomplished by providing a semiconductor package comprising: a semiconductor chip which is formed with a plurality of bond pads at a central portion of its bottom surface; a lead frame including leads connected to bond pads for input/output of the bond pads respectively and bus bars connected to power supplying pads of the bond pads; insulation adhesives for attaching inner leads of the leads and inner leads of the bus bars to a bottom surface of the semiconductor chip formed with the bond pads; metal wires for electrically connecting the inner leads of the leads and the inner leads of the bus bars to the bond pads respectively; and a molding compound enveloping the semiconductor chip assembly with outer leads of the lead frame exposed to outside.
Since the leads of the invention are shortened in length between their inner leads wire-bonded to the bond pads of the semiconductor chip and their outer leads exposed to outside, it is possible to improve lead conductance in a LOC type of semiconductor package and to radiate easily heat occurring in operation of the chip due to their short leads. Particularly, the semiconductor package is appropriate to package a semiconductor chip of 16-mega-bit DRAM or greater which is formed with bond pads at its central portion.
The leads are bent into a certain shape respectively at their inner leads and the outer leads and then the outer leads are attached to polyimide based adhesive tapes. The inner leads of the leads are attached to a bottom surface of the semiconductor chip via insulating films or insulating paste applied to the bottom surface. The attached lead frame and the semiconductor chip are molded such that the outer leads are not protruded from the molded resin but exposed to outside.
In accordance to the invention as described above, paddles are omitted and the outer leads are not protruded from the package but exposed to outside so that the exposed outer leads can be connected to a connection pattern of a printed circuit board. Since the semiconductor package has not protruded outer leads, space occupied by the package is reduced when the package is mounted on a printed circuit board. Also, it is possible to abbreviate trimming and forming procedures next to a molding procedure in its manufacturing process.
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Gaffin Jeffrey
Hyundai Electronics Industries Co,. Ltd.
Loudermilk & Associates
Vigushin John B.
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