Semiconductor package containing multiple memory units

Details Semiconductor package containing multiple memory units Semiconductor package containing multiple memory units

1999-12-22

2002-05-21

Sircus, Brian (Department: 2839)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C361S803000, C439S329000

Reexamination Certificate

active

06392896

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to memory systems for computer systems and, more particularly, relates to semiconductor packages containing multiple memory units on the same ceramic substrate.
Present lay digital computer systems include multiple printed circuit boards on which various integrated and discrete components are mounted as well as other printed circuit boards and single-chip or multi-chip modules. One of these printed circuit boards is called the motherboard. The motherboard usually receives the other printed circuit boards, various integrated and discrete components and the single-chip or multi-chip modules.
In today's more advanced computer systems, the single-chip and multi-chip modules consist of a microprocessor or microprocessors, application specific integrated circuit (ASIC) or other logic device, soldered on a ceramic substrate by controlled collapse chip connections or the like. The module may also contain a cache chip which provides a limited amount (1 megabyte or less) of high speed memory.
Computer memory, specifically random access memory (RAM), often consists of one or more memory modules, such as single in-line memory (SIMM) or dual in-line memory (DIMM) boards which plug into the motherboard or a separate memory board. Such motherboard and separate memory board are made of an organic material such as epoxy impregnated fiberglass. Each memory module may contain one, four or more megabytes of memory. Several memory module sockets are typically provided, not all of which are necessarily occupied. Thus the user can configure the memory system in accordance with the requirements of the computer system, and add additional memory modules, or larger capacity modules, should the memory demands of the system increase.
As computer system speeds and memory requirements increase, computer main memory capacity and complexity have increased. Traditional memory packaging arrangements are becoming inadequate as the disparity between on-chip memory speed and inter-chip communication speed increases.
It would be desirable to have an improved memory packaging arrangement. A number of schemes have been proposed for improving the packaging of memory systems.
Landis U.S. Pat. No. 4,739,446, the disclosure of which is incorporated by reference herein, discloses a connector assembly having pins on the edge for vertically plugging into a board or other connector. The pins extend through the connector assembly to contact a wafer scale assembly.
Landis U.S. Pat. No. 5,034,349, the disclosure of which is incorporated by reference herein, discloses a connector assembly in which a tab connector fans out a metal connection from a bare die silicon chip to an external connector in a planar arrangement.
Angiulli et al. U.S. Pat. No. 5,397,747, the disclosure of which is incorporated by reference herein, discloses a vertical chip mount memory package in which a collection of bare die chip cubes are connected on their edges to a printed circuit board motherboard.
Sanwo et al. U.S. Pat. No. 5,530,623, the disclosure of which is incorporated by reference herein, discloses a high speed memory packaging scheme in which SIMMs and DIMMs are received in connectors which are mounted to a printed circuit board motherboard.
Agusta et al. IBM Technical Disclosure Bulletin, 10, No. 7, pp. 890-891 (December 1967), the disclosure of which is incorporated by reference herein, discloses a high density packaging scheme in which chips mounted on carriers are joined on edge to a module substrate.
Henle IBM Technical Disclosure Bulletin, 20, No. 11A, pp. 4339-4340 (April 1978), the disclosure of which is incorporated by reference herein, discloses a vertical chip packaging scheme in which bare die chips are connected on edge to a substrate by foil strips.
Hermann et al. IBM Technical Disclosure Bulletin, 27, No. 3, pp. 1599-1600 (August 1984), the disclosure of which is incorporated by reference herein, discloses a vertically mounted module in which a set of bare die chips are attached to a SIMM or DIMM which is then soldered directly to a card
In view of the above prior art attempts at improving memory packaging, it is accordingly a purpose of the present invention to have a memory packaging arrangement with increased performance.
It is another purpose of the present invention to mount the memory modules on a ceramic substrate.
It is yet another purpose of the present invention to have a memory packaging arrangement in which the memory modules and microprocessor, ASIC or other logic device are mounted on the same ceramic substrate.
These and other purposes of the present invention will become more apparent after referring to the following description considered in conjunction with the accompanying drawings.
BRIEF SUMMARY OF THE INVENTION
According to a first aspect of the present invention, there is a semiconductor package comprising:
a ceramic substrate;
a planar card having a principal flat surface and at least one edge;
a plurality of memory units mounted on the principal flat surface of the planar card; and
wherein the planar card is mounted edgewise on the ceramic substrate.
According to a second aspect of the present invention, there is a semiconductor package comprising:
a ceramic substrate;
a chip scale package having a first plurality of I/O connections on a surface of the chip scale package and a second plurality of I/O connections on the surface, and at an edge, of the chip scale package, the first and second plurality of I/O connections being connected on the surface of the chip scale package, the chip scale package being mounted edgewise on the ceramic substrate through the second plurality of I/O connections.


REFERENCES:
patent: 4739446 (1988-04-01), Landis
patent: 5034349 (1991-07-01), Landis
patent: 5397747 (1995-03-01), Angiulli et al.
patent: 5530623 (1996-06-01), Sanwo et al.
patent: 6059173 (2000-05-01), Mays et al.
patent: 6115260 (2000-09-01), Nakajima et al.
B. Agusta, et al. “High-Density Packaging of Monolithic Circuits”, IBM Technical Disclosure Bulletin, vol. 10, No. 7, Dec. 1967, pp. 890-891.
R Henle, “Vertical Chip Packaging”, IBM Technical Disclosure Bulletin, vol. 20, No. 11A, Apr. 1978, pp. 4339-4340.
K. Hermann, et al. “Vertically Mounted Module”, IBM Technical Disclosure Bulletine, vol. 27, No. 3, Aug. 1984, pp. 1599-1600.

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