Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2003-02-28
2004-06-15
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S686000
Reexamination Certificate
active
06750545
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
(Not Applicable)
STATEMENT RE: FEDERALLY SPONSORED RESEARCH/DEVELOPMENT
(Not Applicable)
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor packages and, more particularly, to a semiconductor package including a leadframe which is uniquely configured to accommodate stacked semiconductor dies while allowing the resultant semiconductor package to maintain a thin profile.
2. Description of the Related Art
Due to recent advances in the semiconductor packaging arts, there have been developed semiconductor packages fabricated through the use of copper leadframes which are configured in a manner allowing the resultant semiconductor package to have a size which does not substantially exceed that of the semiconductor die mounted to the leadframe. Though being of minimal size, such semiconductor packages possess certain deficiencies which detract from their overall utility.
More particularly, the leadframes of such semiconductor packages are typically configured to allow only a single semiconductor die to be mounted thereto. In certain applications, it is desirable to have multiple semiconductor dies electrically interfaced to a single leadframe. Due to the structural constraints of the small profile leadframes discussed above, the inclusion of multiple semiconductor dies in the semiconductor package necessitates that a first semiconductor die be mounted directly to the leadframe, with a second semiconductor die of identical or reduced size to the first semiconductor die being stacked upon the first semiconductor die. However, such stacking creates difficulties in electrically connecting each of the semiconductor dies to the leads of the leadframe through the use of conductive wires.
Other problems include an excessive increase in the overall thickness of the semiconductor package resulting from the stacking of the semiconductor dies upon each other and upon the leadframe, as well as the reduction in the electrical performance of the semiconductor package attributable to the difficulties in dissipating heat from the semiconductor dies attributable to the stacking thereof. One additional problem lies in the increased length of the signal lines (i.e., the combined lengths of the conductive wires and leads) from the semiconductor dies to an external device, which often results in distortion or deterioration in the characteristics of the transmitted signal. These and other deficiencies of prior art semiconductor packages are alleviated by the present invention which will be described in more detail below.
BRIEF SUMMARY OF THE INVENTION
In accordance with the present invention, there is provided a stackable semiconductor package. The semiconductor package comprises a plurality of first and second leads which are arranged in a generally quadrangular array having one pair of opposed sides defined by the first leads and one pair of opposed sides defined by the second leads. The first and second leads each include opposed, generally planar first and second surfaces, and a third surface which is also disposed in opposed relation to the second surface and positioned between the first and second surfaces. A first semiconductor die is electrically connected to the third surfaces of the first leads, with a second semiconductor die being electrically connected to the third surfaces of the second leads. A package body at least partially encapsulates the first and second leads and the first and second semiconductor dies such that the first and second surfaces of each of the first and second leads are exposed in the package body.
The first and second semiconductor dies in the semiconductor package are arranged in stacked relation to each other, and between the first and second surfaces of each of the first and second leads, thus minimizing the thickness or profile of the semiconductor package. Portions of the first and second leads may be formed to be of variable thickness for purposes of facilitating the electrical connection of the first and second semiconductor dies thereto while in the stacked arrangement.
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Jang Sang Jae
Lee Choon Heung
Lee Sun Goo
Yoshida Akito
Amkor Technology Inc.
Fahmy Wael
Pham Hoai
Stetina Brunda Garred & Brucker
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