Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
1999-09-29
2001-07-10
Booth, Richard (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S111000, C438S124000, C438S125000
Reexamination Certificate
active
06258631
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor package with ultra-multipin structure produced by joining a semiconductor chip to a new leadframe and the manufacturing method.
2. Description of Related Art
FIG. 5
shows a semiconductor package which can be connected to a wiring board and others via an organic substrate provided with a protruded electrode such as a solder ball.
As shown in
FIG. 5
, a semiconductor chip
51
is mounted on the surface of a multilayer organic wiring substrate
50
consisting of two to six layers and formed by organic material. The electrode of this semiconductor chip
51
and a wiring film
52
formed on the surface of the multilayer organic wiring substrate
50
are connected by wire bonding using a gold wire
53
and others for example.
solder ball
55
which functions as a protruded electrode and is electrically connected to the wiring film
52
on the surface via a through hole
54
is provided on the rear of the multilayer organic wiring substrate
50
and this solder ball
55
is protruded from a solder resist film
56
. The semiconductor chip
51
is sealed with sealing resin
57
together with the gold wire
53
.
The solder ball
55
formed on the rear of a semiconductor package
58
constituted as described above is connected to a circuit wiring board
59
. The multilayer organic wiring substrate
50
is often called a ball grid array (BGA) because multiple solder balls
55
are arranged in the shape of a grid and the semiconductor package
58
using this multilayer organic wiring substrate
50
is called BGA package.
There is a limit to reduce pitch between electrode pads on the side of the semiconductor chip
51
because the electrode of the semiconductor chip
51
and the wiring film
52
of the multilayer organic wiring substrate
50
are connected by wire bonding in this BGA package
58
.
There are the following problems because a method of physically placing a so-called solder ball is adopted to form an electrode on the side of the multilayer organic wiring substrate
50
:
(1) When the solder ball
55
is set in a predetermined position, misregistration often occurs.
(2) The size of the solder ball
55
is not fixed because the ball is selected using a sieve, a mesh and others.
(3) There is a limit in reducing the array pitch of the solder balls
55
.
(4) The uniformity of the size of the solder ball
55
and formation by electroplating which enables the reduction of pitch are disabled because the base of the multilayer organic wiring substrate
50
is a base material.
(5) There is a limit to the composition of the solder ball
55
.
Therefore, this applicant proposed a semiconductor package provided with ultra-multipin structure formed by joining a new leadframe and a semiconductor chip.
FIG. 6
shows the structure of this semiconductor package and the semiconductor package is manufactured as follows:
First, to manufacture a semiconductor package
60
shown in
FIG. 6
, multiple leads
61
are formed on the surface of a metallic base not shown in FIG.
6
and prepared beforehand by copper electroplating, a polyimide film
62
for holding each lead
61
in a part except the inner lead section
61
a
is formed and further, a solder resist film
63
is formed.
Next, a protruded electrode
64
is formed in the outer lead section
61
b
of each lead
61
by electroplating, afterward the metallic base is selectively removed with the peripheral coupled portion left and hereby, a leadframe
65
in which each lead
61
is separated is obtained.
Next, a semiconductor chip
67
is joined to the inner lead section
61
a
of the lead
61
via a bump
66
and afterward, the body of a package
69
is stuck on the rear of the lead
61
except the inner lead section
61
a
via an adhesive layer
68
. Finally, the semiconductor chip
67
housed in the body of the package
69
is sealed with resin
70
and further, an individual semiconductor package
60
is obtained by removing the coupled portion of the leadframe
65
. In this case, multiple protruded electrodes
64
are formed and arranged in the shape of a grid around the semiconductor chip
67
.
According to this semiconductor package
60
, the lead
61
can be minutely patterned by forming the lead
61
and the protruded electrode
64
by electroplating using the metallic base. The protruded electrode
64
is formed in a right position, the size of each protruded electrode
64
is unified, pitch between protruded electrodes
64
can be reduced and the miniaturization of LSI and increasing the number of pins to ultra-multipin structure are enabled.
However, in the constitution of this semiconductor package
60
, as the polyimide film
62
for reinforcing a lead and the solder resist film
63
for protecting a lead are overlapped on the lead
61
and difference in a level is made in the overlapped portion, there are the following problems:
That is, as a portion formed by the overlapped polyimide film
62
and solder resist film
63
is locally a cavity as shown in
FIG. 7
, the lead
61
is locally etched because of the existence of the hollow portion
71
and disconnection may be caused if the metallic base is selectively etched in the package manufacturing process.
When the solder plated ball is formed, a chemical such as a plating agent infiltrates from a location shown by a letter A in
FIG. 7
, is collected in the hollow portion
71
, the failure of deposition occurs around it and an alloy layer may be formed. As this alloy layer produced due to the failure of deposition is formed between leads
61
and is left without being etched even when the metallic base is selectively etched, it causes a short circuit between the leads.
Further, in the final leadframe cleaning process, a chemical such as a plating agent is left and it causes stain and failure.
SUMMARY OF THE INVENTION
A semiconductor package according to the present invention is provided with the body of a package in which a chip housing concave portion is formed on the side of the lead joined face, a semiconductor chip housed and fixed in the chip housing concave portion in the body of this package, a plurality of leads joined on the lead joined face of the body of the package and held, the inner lead section of which is joined to the semiconductor chip via a bump and in the outer lead section of which a protruded electrode is formed, a lead protective coat formed on the lead except the bump formed area and the electrode formed area of this lead and a lead reinforcing film formed on the side of the inner lead section of the lead on the lead protective coat.
A method of manufacturing the semiconductor package according to the present invention is provided with a process in which a plurality of leads are formed by copper plating on the surface of a metallic base formed by laminating an etching stopping film and a plating substrate film on a substrate consisting of copper or a copper alloy in order, a process in which a lead protective coat is formed on the lead formed surface of the metallic base except the bump formed area and the electrode formed area of the lead, a process in which a lead reinforcing film is formed on the side of the inner lead section of the lead on the lead protective coat, a process in which a protruded electrode is formed iii the outer lead section of the lead, a process in which each lead is separated by selectively removing the metallic base by etching and a process in which a semiconductor chip is joined to the inner lead section of the lead.
As in the present invention, a lead protective coat is formed on a plurality of leads except the respective bump formed area and the respective electrode formed area and a lead reinforcing film is formed on this lead protective coat, no difference in a level made by the overlap of films is formed on a lead differently from a case according to the prior art. Therefore, as no local cavity exists on the lead and no collection of a chemical by the infiltration of the chemical from a portion with difference in a level al
Ito Makoto
Ohsawa Kenji
Booth Richard
Simkovic Viktor
Sonnenschein Nath & Rosenthal
Sony Corporation
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