Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Including adhesive bonding step
Reexamination Certificate
2001-04-11
2002-04-16
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Including adhesive bonding step
C438S118000, C438S106000, C438S107000, C438S108000, C257S678000, C257S684000, C257S701000
Reexamination Certificate
active
06372549
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor package wherein an interposer (wiring base material) that is provided with a wiring layer having a prescribed wiring pattern on an insulating base material is adhered to an electrode formation surface of a semiconductor chip by means of an adhesive layer; the wiring layer and electrodes of the semiconductor chip connect by way of bump contacts (bump electrodes); i.e., are electrically connected by the flip-chip method; and external connectors are provided on the surface of the wiring layer that is opposite from the surface that is joined to the semiconductor chip. The present invention also relates to a fabrication method of such a semiconductor package.
2. Description of the Related Art
The research and development of higher-density semiconductor device packages is currently making great strides, and many configurations and methods have been proposed for the configuration of a package. In particular, a high-density semiconductor package known as a Chip Scale Package (CSP) in which the package size has been miniaturized to a size that is substantially equal to chip size is receiving attention, and a variety of developments have been achieved.
The form of a semiconductor package that is suitable for constructing a CSP is:
a semiconductor package in which an interposer, in which a wiring layer of, for example, copper wiring having a prescribed wiring pattern is arranged on an insulating base material such as polyimide tape, is adhered to the electrode formation surface of a semiconductor chip by way of an adhesive layer; electrodes, such as aluminum electrodes, of the semiconductor chip are electrically connected to a wiring layer by way of bumps such as gold ball bumps; i.e., by the so-called flip-chip method; and external connectors are provided on the side of the wiring layer that is opposite from the junction surface with the semiconductor chip. In this case, external connectors are, for example, solder balls that are attached to lands of the wiring layer or similar lands.
Semiconductor packages of the prior art having this type of construction can be classified into two types according to the positional relation between the semiconductor chip, the insulating base material, the wiring layer, and the adhesive layer. The first type is characterized by a configuration in which the positioning order is: semiconductor chip, adhesive layer, insulating base material, and wiring layer. The second type is a configuration in which the positioning order is: semiconductor chip, adhesive layer, wiring layer, and insulating base material.
Prior art that belongs to the first type is disclosed in the explanation pertaining to FIG. 2 and FIG. 4 of Japanese Patent Laid-open No. 321157/95, and in the explanation pertaining to FIG. 4 and FIG. 9 of Japanese Patent Laid-open No. 102474/96. Prior art that belongs to the second type is disclosed in the explanation pertaining to FIG. 1 and FIG. 3 of Japanese Patent Laid-open No. 321157/95, and in the explanation pertaining to FIG. 3 and FIG. 8 of Japanese Patent Laid-open No. 102474/96.
Turning now to the accompanying figures, explanation is next presented regarding the construction and fabrication method of semiconductor packages of the above-described first type and second type.
FIG. 1
shows a sectional view of semiconductor package
2
of one example of the prior art, and
FIG. 2
is an enlarged view of portion B in FIG.
1
.
This semiconductor package
2
of the prior art is the above-described first type of semiconductor package and has a construction in which semiconductor chip
21
is applied to wiring tape
5
by means of adhesive layer
26
. As shown in
FIG. 2
, this portion is constructed by laminating in the order: semiconductor chip
21
, adhesive layer
26
, insulating film
23
as the insulating base material, copper wiring
24
as the wiring layer, and cover resist
29
that insulates and covers copper wiring
24
.
Chip electrodes
22
and copper wiring
24
are electrically connected by way of filled copper bumps
27
that fill holes that are formed in adhesive layer
26
and insulating film
23
. Gold plating (not shown in the figures) is applied to the contacting surfaces of chip electrodes
22
and filled copper bumps
27
to form gold-gold metal junctions. Cover resist
29
is provided with holes
29
b
at positions where solder balls
28
are attached as the external terminals, and is provided with holes
29
a
at positions that correspond to chip electrodes
22
. Solder balls
28
contact copper wiring
24
at holes
29
b
. Reinforcement resin
30
is formed on wiring tape
5
around the periphery of semiconductor chip
21
.
When assembling semiconductor package
2
, the adhesive surface that is formed by adhesive layer
26
of wiring tape
5
is temporarily secured on the electrode formation surface of semiconductor chip
21
on which chip electrodes
22
are formed; bonding tool
50
is passed through holes
29
a
and placed in contact with copper wiring
24
, and pressure and ultrasonic waves are applied to the connector portion (inner lead connectors) chip electrode
22
and filled copper bumps
27
. In a case in which semiconductor chip
21
is provided with, for example, 1000 chip electrodes
22
, this bonding operation by means of bonding tool
50
must be carried out a total of 1000 times.
Next, complete adhesion between semiconductor chip
21
and wiring tape
5
can be obtained by applying appropriate heat and pressure to adhesive layer
26
.
The construction and method of fabricating a semiconductor package of the second type is next explained with reference to the figures.
FIG. 3
shows a sectional view of semiconductor package
3
of an example of the prior art, and
FIG. 4
shows an enlarged view of portion C in FIG.
3
.
This prior-art semiconductor package
3
is a semiconductor package of the second type, and has a construction in which semiconductor chip
31
and wiring tape
6
having adhesive layer
36
are adhered together. As shown in
FIG. 4
, a section of this semiconductor package
3
is of a construction in which semiconductor chip
31
, adhesive layer
36
, copper wiring
34
as the wiring layer, and insulation film
33
as insulating base material are laminated in that order. In contrast with semiconductor package
2
of the first type, copper wiring
34
is covered by insulating film
33
and adhesive layer
36
, and a cover resist is therefore not used.
Chip electrodes
32
and copper wiring
34
are electrically connected by way of gold ball bumps
37
that are inserted into holes that are formed in adhesive layer
36
. Gold plating (not shown in the figures) is applied to the surfaces of copper wiring
34
that contact the gold ball bumps so as to form a gold-gold metal junction. In insulating film
33
, holes
33
b
are provided at the positions at which solder balls
38
are arranged as external terminals, and holes
33
a
are provided at positions that correspond to chip electrodes
32
. Solder balls
38
contact copper wiring
34
in holes
33
b.
When assembling semiconductor package
3
, the adhesive surface that is arranged on adhesive layer
36
of wiring tape
6
is temporarily secured to the electrode formation surface of semiconductor chip
31
upon which gold ball bumps
37
are arranged at chip electrodes
32
, i.e., temporarily secured on the surface on which chip electrodes
32
are formed; and bonding tool
50
is passed through holes
33
a
and placed against copper wiring
34
, following which pressure and ultrasonic waves are applied to the connectors (inner lead connectors); i.e., between gold ball bumps
37
and chip electrodes
32
and between gold ball bumps
37
and copper wiring
34
. In a case in which, for example, 1000 chip electrodes
32
are provided on semiconductor chip
31
, this bonding operation by bonding tool
50
must be performed a total of 1000 times.
An appropriate degree of heat and pressure are then applied to adhesive layer
36
to obtain complete
Geyer Scott B.
Sughrue & Mion, PLLC
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