Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2005-05-12
2010-10-05
Monbleau, Davienne (Department: 2893)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S730000, C257S787000, C257SE23043, C257SE23049, C257SE23066
Reexamination Certificate
active
07808096
ABSTRACT:
A semiconductor package production method includes the step of die-cutting part of a lead side portion of a seal formed by molding and dam bars using a pedestal and punch. The pedestal has an outer surface at a position retreating from a side surface of an upper seal portion as far as possible and an inner surface generally near a side surface of a lower seal portion. Width Wa of the upper surface of the upper surface of the pedestal is smaller than the overhang size of the upper seal portion. Tip end region Ra of the lead side portion which is present right under the overhang portion of the upper seal portion has a slanted surface Fa1which is sloped inwardly from top to bottom.
REFERENCES:
patent: 6696753 (2004-02-01), Tokuhara
patent: 2004/0212049 (2004-10-01), Fukatani et al.
patent: 06-120375 (1994-04-01), None
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patent: 2002-94035 (2002-03-01), None
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Japanese Office Action, with English translation, issued in Japanese Patent Application No. 2004-230712, mailed Nov. 24, 2009.
Hirano Tatsuya
Inao Hisaho
Shimizu Katsutoshi
McDermott Will & Emery LLP
Monbleau Davienne
Nguyen Dilinh P
Panasonic Corporation
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