Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package
Reexamination Certificate
2001-02-20
2003-09-09
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
C257S700000, C257S758000, C257S738000, C257S701000, C257S620000, C257S618000, C257S784000, C257S773000, C257S780000, C438S106000, C438S127000, C438S125000, C438S460000, C438S612000, C438S613000, C438S614000
Reexamination Certificate
active
06617674
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor package and more particularly to a wafer-level semiconductor package containing a cured silicone layer. The present invention also relates to a method of preparing the semiconductor package.
BACKGROUND OF THE INVENTION
Integrated circuit (IC) chips or dice are commonly packaged before assembly on a printed wiring board (PWB). The package has several important functions, including interconnection (power and signal transmission), mechanical and environmental protection, and heat dissipation. In addition, the package acts as a mechanism for “spreading apart” the connections from the tight pitch (center to center spacing between bond pads) on the IC chip to the relatively wide pitch required by the printed circuit board manufacturer.
In the highly competitive market of electronic packaging, factors of performance, throughput, cost, and reliability have a major influence on packaging technologies. Although packaging is usually performed on individual IC chips, there is growing interest in developing methods of packaging ICs at the wafer level, (i.e., before singulation of individual chips from the wafer). Wafer-level packaging can potentially achieve higher throughput, higher reliability, and lower costs than individual chip packaging.
The reliability of IC packages is often limited by failure of the interconnect elements (e.g., solder joints, bond wires) between the die and the package substrate or between the package and the PWB. Because such failures are often due to differences in coefficients of thermal expansion (CTE) between the silicon die, the substrate, and the PWB materials, various approaches to minimizing thermally induced stresses in semiconductor packages have been reported. For example, U.S. Pat. No. 5,171,716 to Cagan et al. discloses a semiconductor device containing a stress-relief layer having a glass transition temperature below 150° C.
Kang et al. teach a wafer-level chip scale package containing a high CTE/modulus dielectric polymer as a stress buffer layer (Electronic Components and Technology Conference Proceedings, 2000, 87-92).
Strandjord et al. teach a one mask process for stress-buffer and passivation applications using photosensitive benzocyclobutene (IEMT/IMC Symposium Proceedings, 1997, 261-266).
U.S. Pat. No. 6,103,552 discloses a process and a package for wafer-scale packaging. The process includes depositing a layer of a polymeric material, such as polyimide, silicone elastomer, or benzocyclobutene on the surface of a chip. The '552 patent further teaches that the temperature coefficient of expansion of the polymer should be low so as to match that of the metal studs in the package, thereby minimizing local stresses at the stud-polymer interface.
Although the aforementioned approaches to semiconductor packaging provide packages having a range of thermal properties, there is a continued need for a semiconductor package having superior thermal stability.
SUMMARY OF THE INVENTION
The present invention is directed to a semiconductor package comprising:
a semiconductor wafer having an active surface comprising at least one integrated circuit, wherein each integrated circuit has a plurality of bond pads; and
a cured silicone layer covering the active surface, provided at least a portion of each bond pad is not covered by the silicone layer and wherein the silicone layer is prepared by a method comprising the steps of:
(i) applying a silicone composition to the active surface to form a film, wherein the silicone composition comprises:
(A) an organopolysiloxane containing an average of at least two silicon-bonded alkenyl groups per molecule,
(B) an organosilicon compound containing an average of at least two silicon-bonded hydrogen atoms per molecule in a concentration sufficient to cure the composition, and
(C) a catalytic amount of a photoactivated hydrosilylation catalyst;
(ii) exposing a portion of the film to radiation having a wavelength of from 150 to 800 nm to produce a partially exposed film having non-exposed regions covering at least a portion of each bond pad and exposed regions covering the remainder of the active surface;
(iii) heating the partially exposed film for an amount of time such that the exposed regions are substantially insoluble in a developing solvent and the non-exposed regions are soluble in the developing solvent;
(iv) removing the non-exposed regions of the heated film with the developing solvent to form a patterned film; and
(v) heating the patterned film for an amount of time sufficient to form the cured silicone layer.
The present invention is further directed to a method of preparing a semiconductor package, the method comprising the steps of:
(i) applying a silicone composition to an active surface of a semiconductor wafer to form a film, wherein the active surface comprises at least one integrated circuit, each integrated circuit has a plurality of bond pads, and the silicone composition comprises:
(A) an organopolysiloxane containing an average of at least two silicon-bonded alkenyl groups per molecule,
(B) an organosilicon compound containing an average of at least two silicon-bonded hydrogen atoms per molecule in a concentration sufficient to cure the composition, and
(C) a catalytic amount of a photoactivated hydrosilylation catalyst;
(ii) exposing a portion of the film to radiation having a wavelength of from 150 to 800 nm to produce a partially exposed film having non-exposed regions covering at least a portion of each bond pad and exposed regions covering the remainder of the active surface;
(iii) heating the partially exposed film for an amount of time such that the exposed regions are substantially insoluble in a developing solvent and the non-exposed regions are soluble in the developing solvent;
(iv) removing the non-exposed regions of the heated film with the developing solvent to form a patterned film; and
(v) heating the patterned film for an amount of time sufficient to form a cured silicone layer.
The semiconductor package of the present invention exhibits good thermal stability over a wide range of temperatures and good environmental resistance. Also, the semiconductor package permits simultaneous testing of all ICs on a wafer. Moreover, individual chips can be singulated (separated) from the wafer-level semiconductor package, with each chip having a size only slightly larger than the IC itself. These “chip scale packages”, which are lighter, smaller, and thinner than conventional IC packages, are ideally suited for high-density applications.
The method of preparing the semiconductor package of the present invention is scaleable to a high throughput manufacturing process. Importantly, the method provides simultaneous packaging of all ICs on a wafer. Additionally, the method employs conventional wafer fabrication techniques (e.g., coating, exposing, developing, curing) and equipment. Furthermore, the method uses a photopatternable silicone composition, thereby eliminating additional process steps associated with use of a non-photopatternable polymer composition. Finally, the process of the instant invention has high resolution, meaning that the process transfers images from a photomask to the silicone layer on a wafer with good retention of critical dimensions.
The semiconductor package of the present invention can be used to prepare individual IC chip packages. The chip packages are useful for fabricating printed wiring boards, which can be incorporated into electronic equipment, such as calculators, telephones, televisions, and mainframe and personal computers.
These and other features, aspects, and advantages of the present invention will become better understood with reference to the following description, appended claims, and accompanying drawings.
REFERENCES:
patent: 3723497 (1973-03-01), Baney
patent: 4064027 (1977-12-01), Gant
patent: 4939065 (1990-07-01), Cavezzan et al.
patent: 5008733 (1991-04-01), Mine et al.
patent: 5045918 (1991-09-01), Cagan et al.
patent: 5145886 (1992-09-01), Oxman et al.
patent: 5171716 (19
Becker Gregory Scott
Gardner Geoffrey Bruce
Harkness Brian Robert
Malenfant Louise Ann
Sarmah Satyendra Kumar
Brown Catherine U.
Dow Corning Corporation
Milco Larry A.
Williams Alexander O.
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