Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material
Reexamination Certificate
2002-03-29
2004-12-28
Thai, Luan (Department: 2829)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Insulating material
C257S787000, C257S788000, C257S779000
Reexamination Certificate
active
06836012
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-101840 filed on Mar. 30, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor package and a method of manufacturing the semiconductor package. In particular, the present invention relates to a technique of improving the reliability of outer lead bonding (OLB) parts of a semiconductor device.
2. Description of the Related Art
As shown in
FIGS. 1A and 1B
, the wiring layer
30
is formed on a package base
20
and is connected to the semiconductor chip
10
through the contacts
13
. These contacts
13
are inner lead bonding (ILB) parts that are sealed with the underfill resin layer
40
. The underfill resin layer
40
is extended to the edge of the package. In
FIG. 1B
, the package is mounted on the board
80
with solder
75
.
In
FIG. 2A
, a package base
20
is provided with ILB parts
13
, a wiring layer
30
, and package terminals
70
and is covered with an underfill resin layer
40
. In
FIG. 2B
, a semiconductor chip
10
is placed, and electrode terminals of the chip
10
are connected to the wiring layer
30
through the ILB parts
13
. In
FIG. 2C
, the semiconductor chip
10
and underfill resin layer
40
are sealed with a resin mold
60
.
As shown in
FIGS. 3A and 3B
, the package of
FIG. 3A
differs from the package of
FIG. 1A
in that it employs no underfill resin and seals contacts (ILB parts
13
) between a semiconductor chip
10
and a wiring layer
30
with a resin mold
60
.
In
FIG. 4A
, a package base
20
is provided with ILB parts
13
, a wiring layer
30
, and package terminals
70
. In
FIG. 4B
, a semiconductor chip
10
is set without underfill resin and electrode terminals of the chip
10
are connected to the wiring layer
30
through the ILB parts
13
. In
FIG. 4C
, the semiconductor chip
10
, package base
20
, wiring layer
30
, and ILB parts
13
are sealed with a resin mold
60
.
The underfill resin layer
40
of
FIG. 1A
must have the following properties:
(1) a high fluidity to collectively seal the ILB parts
13
;
(2) a low thermal expansion coefficient &agr; to improve the reliability of the ILB parts
13
; and
(3) a low elasticity modulus E, i.e., softness to improve the reliability of OLB parts, the OLB parts corresponding to contacts between the wiring layer
30
and the package terminals
70
.
Generally, a resin having a low thermal expansion coefficient &agr; has a high elasticity modulus E, and a resin having a high thermal expansion coefficient &agr; has a low elasticity modulus E. There are resins such as a no conductive film (NCF) having a low thermal expansion coefficient &agr; and a low elasticity modulus E. This type of resin, however, is expensive.
A semiconductor package employing an underfill resin layer involves the following problems:
(1) low reliability of OLB parts if the underfill resin layer has a low thermal expansion coefficient &agr; and a high elasticity modulus E to secure the reliability of ILB parts;
(2) low reliability of the ILB parts if the underfill resin layer has a high thermal expansion coefficient &agr; and a low elasticity modulus E to secure the reliability of the OLB parts; and
(3) increase cost of the package if the underfill resin layer is made from, for example, an NCF to secure the reliability of both the ILB and OLB parts.
The semiconductor package of
FIG. 3A
is advantageous in that it:
(1) employs no underfill resin layer, reducing process and material costs; and
(2) employs the resin mold
60
, which generally has a low thermal expansion coefficient &agr;, thus improving the reliability of the ILB parts
13
.
The package of
FIG. 3A
, however, is disadvantageous in that:
(3) the reliability of the OLB parts is reduced, due to the hardness of the resin mold
60
having a high elasticity modulus E. Namely, the high elasticity modulus of the resin mold
60
on the package terminals
70
causes a concentration of strain at the OLB parts. If the package having no underfill resin layer is large, the reliability of the OLB parts falls critically. In this case, the underfill resin layer must be prepared to improve the reliability of the OLB parts.
When semiconductor packages are diced into individual packages, inferior adhesion between a resin mold and a wiring layer in a package causes a further problem of separating the resin mold from the wiring layer at the edge of the package.
Namely, the semiconductor package having no underfill resin layer involves the following problems:
(1) low reliability of OLB parts; and
(2) peeling on the side faces of the package.
SUMMARY OF THE INVENTION
According to an embodiment of the present invention, a semiconductor package includes (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer. The low-elasticity resin layer has a lower elasticity modulus than the resin mold.
According to another embodiment of the present invention, a semiconductor package manufacturing method includes (a) forming a wiring layer on a package base, (b) electrically connecting a semiconductor chip to the wiring layer, (c) forming a low-elasticity resin layer having a lower elasticity modulus than a resin mold, onto the package base and the wiring layer, and (d) forming the resin mold on the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.
REFERENCES:
patent: 5874784 (1999-02-01), Aoki et al.
patent: 5990546 (1999-11-01), Igarashi et al.
patent: 6166433 (2000-12-01), Takashima et al.
patent: 6340793 (2002-01-01), Yaguchi et al.
patent: 08-078574 (1996-03-01), None
patent: 2000-164761 (2000-06-01), None
patent: 2001-127095 (2001-05-01), None
U.S. Appl. No. 09/854,559, filed May 15, 2001, to Funakura et al.
Fukuda Masatoshi
Funakura Hiroshi
Hosomi Eiichi
Kawai Kaoru
Koshio Yasuhiro
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Thai Luan
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