Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
2000-04-25
2002-03-12
Picardat, Kevin M. (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C438S106000, C438S111000, C438S123000
Reexamination Certificate
active
06355502
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method for making a semiconductor package, and more particularly to a method for making a semiconductor package and its carrier structure.
2. Description of Related Art
As far as the development of integrated circuit technology is concerned, not only it is heading for ever high integration in the front-end process, but it is also in pursuit of a package with ever high density in the back-end process of the semiconductor industry. The Chip Scale Package (CSP) which is actively developed and manufactured by the industry nowadays has its package size only slightly larger than that of the chip. Therefore, the CSP not only can save a lot of space, but since the signal transmission path is shorten, the CSP can also increase the efficacy of the product. The carrier employed by the CSP includes a lead frame, a flexible substrate, and a rigid substrate etc. Moreover, the lead frame having the advantage of low in cost and easy in working becomes a popular CSP package type in the consumer electronic products. For instance, the popular lead frame based CSPs are Quad Flat Nolead (QFN) Package developed by Matsusita, Micro Lead Frame Package (MLP) developed by Amkor, and Bottom Leaded Package (BLP) developed by LG electronics etc. In addition, the leadless type of CSP having the advantages of shortening the signal transmission path and lowering the signal attenuation is always a popular package structure of the low pin count semiconductor device.
FIG. 1
is a cross-sectional view of a QFN package according to a prior art, and
FIG. 2
is a top view of the QFN package in FIG.
1
. The technology of QFN package structure has been disclosed in U.S. Pat. No. 5,942,794 (Matsushita, 1999). The QFN package structure
120
is constructed on a lead frame that includes a die pad
100
and a plurality of leads
102
. The leads
102
having an upper surface
118
a
, a lower surface
118
b
, and a side surface
118
c
are disposed on the periphery of the die pad
100
. A chip
104
having an active surface
106
and a back surface
108
is attached to the die pad
100
by the back surface
108
with an adhesive
112
. A plurality of bonding pads
110
built on the active surface
106
and served as the external connections of the chip
104
is electrically connected to the leads
102
by the bonding wires
114
. A molding compound
116
is then used to encapsulates the chip
104
, the die pad
100
, the bonding wire
114
, and the upper surface
118
a
of the lead
102
while to expose the lower surface
118
b
and the side surface
118
c
of the lead
102
to serve as the external connections of the whole package
120
. A singulating process is then performed to separate the packages from the lead frame after the encapsulating process is accomplished.
The singulating process either using the sawing process or the punching process for the lead frame type semiconductor package disregarding whether it is a QGN, a MLP, or a BLP as mentioned above will directly impact the outer lead portion (not shown) of the lead
102
. This impact not only results in the shortening in the service life of the facilities, the impairing of the products' integrity, but also the delaminating between the leads
102
and the molding compound
116
. Consequently, the moisture sensitivity level of the products is deteriorated and the reliability of the products is affected.
SUMMARY OF THE INVENTION
The invention is directed to an improved semiconductor package process that can improve the product's integrity.
The invention is also directed to an improved semiconductor package process that can prolong the product's service life and can facilitate the mass production of the product.
The invention is further directed to an improved semiconductor package process that can increase the reliability of the product.
In order to attain the foregoing and other object of improvement, the present invention presents a method for making a semiconductor package that firstly provides a lead frame having a first surface and a corresponding second surface, and the lead frame includes at least a package unit. The package unit further includes a die pad, and a plurality of leads disposed on the periphery of the die pad where each of the leads further includes a neck portion. The method then attaches the second surface of the lead frame to a tape, and performs a punching process to cut off the neck portion of the lead so as to form a plurality of conductive blocks disposed independently on the periphery of the die pad. The method further provides a chip having its back surface attach to the first surface of the die pad, and electrical connection between the bonding pad and the first surface of the conductive block by using a plurality of bonding wires. Further, the method performs an encapsulating process to encapsulate the chip, the bonding wires, the die pad, and the first surface of the conductive block. The method then performs singulating process to separate the package unit from the lead frame. Finally the method performs a detaping process to expose the die pad and the second surface of the conductive block.
According to a preferred embodiment of the present invention, a V-shaped notch is formed beforehand on the second surface of the neck portion of the lead to facilitate the cutting off during the subsequent punching process. Besides, the lead can be designed to have an embedded structure to be embedded in the molding compound in order to avoid being separated. The embedded structure can be designed to have the area of the first surface of the lead larger than the area of the second surface of the lead such that the side surfaces become inclined planes, or to have the side surfaces form recess structure. The purpose of the design is that the first surface of the lead can be embedded in the molding compound while the second surface of the lead is exposed to the air, or the recesses can be filled by the molding compound so as to enhance the embedding effect.
Since the lead is separated from the lead frame in the previous punching process, the tool does not impact the lead frame directly during the singulating process. Therefore, the semiconductor package of the present invention can improve the integrity of the product, prolong the service life of the facilities. It can even avoid the occurrence of delaminating phenomenon, improve the moisture sensitivity level, and increase the reliability of the product.
Furthermore, in order to attain the foregoing and other objectives of improvement, the present invention also provides a lead frame structure for the process of the present invention. The lead frame structure having a first surface and a corresponding second surface includes at least a package unit. The package unit having a die pad, and a plurality of leads disposed on the periphery of the die pad further includes a neck portion wherein the width of the neck portion is smaller than the width of the other portion of the lead.
REFERENCES:
patent: 5885852 (1999-03-01), Kishikawa et al.
patent: 6177719 (2001-01-01), Huang et al.
Kang Kun-A
Lee J. H.
Park Hyung J.
Collins D. M.
Huang Jiawei
J.C. Patents
National Science Council
Picardat Kevin M.
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