Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package
Reexamination Certificate
2002-11-26
2004-04-06
Enad, Elvin (Department: 2832)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
C257S738000, C257S780000, C257S787000, C438S112000, C438S118000
Reexamination Certificate
active
06717248
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor package and method for fabricating the same.
2. Discussion of Related Art
Semiconductor packages such as ball grid array (BGA) package, chip scale package and micro ball grid array package reflect the trend towards of miniaturization and thinness in packaging. Furthermore, today's semiconductor chips are generating increasing amounts of heat during the operation of the semiconductor chip.
FIG. 16
illustrates a conventional BGA semiconductor package. A semiconductor chip
2
′ having a plurality of electronic circuits integrated therein and input/output pads
4
′ thereon is mounted at the center of the top face of a relatively thick printed circuit board
10
′. An adhesive layer
91
′ attaches chip
2
′ to circuit board
10
′. Printed circuit board
10
′ is composed of a resin film
11
′ as a base layer. Resin film
11
′ has a circuit pattern layer including bond fingers
12
′, connector parts
13
′ (e.g., conductive traces) formed on the top side thereof, and ball lands
15
′ in grid shape formed on the bottom side thereof. The circuit pattern layer is formed around semiconductor chip
2
′ in radial form. Bond fingers
12
′, connection parts
13
′ and ball lands
15
′ constituting the circuit pattern layer are formed from a conductive metal material such as copper or the like. Connection parts
13
′ located on the top of resin film
11
′ and ball lands
15
′ disposed on the bottom thereof are electrically connected to each other through a conductive via hole
14
′. A portion of the top and bottom sides of resin film
11
′, other than the region on which bond fingers
12
′, ball lands
15
′ and semiconductor chip
2
′ are disposed, is coated with a cover coat
16
′ to protect the circuit pattern layer from external environment and prevent short-circuiting.
Moreover, input/output pads
4
′ of semiconductor chip
2
′ are connected to bond fingers
12
′ formed on printed circuit board
10
′ through conductive wires
6
′. The upper side of printed circuit board
10
′, including semiconductor chip
2
′, is encapsulated with an encapsulant
20
′ so as to protect semiconductor chip
2
′, conductive wires
6
′ and their bonded portions from harmful external environments. Conductive balls
30
′ are fused to ball lands
15
′ formed on the bottom face of printed circuit board
10
′ so as to be able to transmit electric signals between semiconductor chip
2
′ and a mother board (not shown) when semiconductor chip
2
′ is mounted on the mother board.
In such a conventional BGA semiconductor package, electric signals from semiconductor chip
2
′ are delivered to the mother board through input/output pads
4
′, conductive wires
6
′, bond fingers
12
′, connection parts
13
′, via hole
14
′, ball lands
15
′ and conductive balls
30
′ sequentially, or they are transmitted reversely. However, in the conventional BGA package, semiconductor chip
2
′ is mounted on the top of relatively thick printed circuit board
10
′, which increases the thickness of the semiconductor package and makes it unsatisfactory in applications requiring a small and thin semiconductor package. Consequently, the conventional BGA package is not suitable for small electronic devices such as cellular phone and pager.
Further, as described above, the amount of heat generated per unit volume during the operation of the semiconductor chip is relatively high, but the heat spreading efficiency is low, which deteriorates the electrical performance of the semiconductor chip and, according to circumstances, may lead to failure. There has been proposed a semiconductor package having a heat spreading plate for easily emitting heat generated during the operation of the semiconductor chip. In this case, however, mounting of the heat spreading plate increases the thickness of the semiconductor package and manufacturing cost.
Meanwhile, the currently manufactured semiconductor package is generally 5×5 mm in area and 1 mm in thickness. Accordingly, a circuit board strip capable of simultaneously fabricating tens to hundreds of semiconductor packages has not been realized so far, even though it is ideal for as many semiconductor packages as possible to be made from a single circuit board strip with a conventional size. This is because of poor wire bonding due to warpage caused by a difference in the thermal expansion coefficients between different materials constituting the circuit board strip, inferior molding, and/or damage to the semiconductor chip due to momentary discharging of static electricity accumulated during the molding process.
FIG. 17
is a bottom view illustrating a conventional semiconductor package using a circuit board unit
10
′ having a runner gate. With reference to
FIG. 17
, runner gate RG is formed at a corner of circuit board unit
10
′. Runner gate RG functions as a passage through which a melted molding resin at a high temperature and pressure is poured into the package for forming a resin encapsulant
20
′ that protects semiconductor
2
′ from the external environment. Conductive balls
30
are formed as external input/output terminals after the molding step.
FIG. 18
is a cross-sectional view illustrating a molding step in the fabrication of the conventional semiconductor package. Referring to
FIG. 18
, semiconductor chip
2
′ is mounted on printed circuit board unit
10
′. Wire bonds
6
′ are attached between a circuit pattern formed on unit
10
′ and semiconductor chip
2
. The assembly is located between a top die TD and bottom die BD, which is filled with melted resin encapsulant
20
. Specifically, top die TD has a cavity CV with a predetermined-size space so that encapsulant
20
′ can encapsulate semiconductor chip
2
′ therein. Cavity CV is connected to a gate G and runner R (corresponding to runner gate RG of
FIG. 17
) to allow melted encapsulant
20
′ to flow from a resin port (not shown) through runner R and gate G to cavity CV. Runner gate RG is conventionally composed of a plated region using gold.
The conventional method of fabricating a semiconductor package, as mentioned above, has a shortcoming in that the runner gate should be formed on one side of the circuit board in the step of molding. This runner gate raises the manufacturing cost of the package because it is formed by plating a metal such as gold whose strength of adhesion to the encapsulant is smaller than that of the circuit board. Further, any increase in the number of or change in the location of the conductive balls
30
′ is limited since the ball lands cannot be formed at the runner gate region.
Moreover, providing a mold having the runner and gate with a shape corresponding to the runner gate of the circuit board, i.e., top die, can be complicated and costly. In addition, if the runner gate of the circuit board during molding, it is possible that the melted encapsulant will bleed out toward the ball lands. This obstructs the fusing of conductive balls
30
′ to the ball lands.
U.S. Pat. No. 5,620,928 provides another example of a conventional package.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a semiconductor package and method for fabricating the same that substantially obviates limitations and disadvantages of the related art.
A first objective of the present invention is to provide a very thin semiconductor package.
A second objective of the present invention is to provide a semiconductor package having excellent heat spreading performance.
A third objective of the present invention is to provide a semiconductor package having excellent heat spreading performance, wherein the backside of the chip may be grounde
Chun Do Sung
DiCaprio Vincent D.
Jang Tae Hoan
Lee Seon Goo
Shin Won Sun
Amkor Technology Inc.
Bever Hoffman & Harms LLP
Enad Elvin
Lee K.
Parsons James E.
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