Semiconductor package and method for fabricating the same

Details Semiconductor package and method for fabricating the same Semiconductor package and method for fabricating the same

2000-05-19

2002-05-28

Bowers, Charles (Department: 2825)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S108000, C438S123000, C438S613000, C438S615000, C438S617000

Reexamination Certificate

active

06395578

ABSTRACT:

BACKGROUND OF THE INVENTION
I. Field of the Invention
The present invention relates to a semiconductor package and a method for fabricating the semiconductor package.
II. Description of the Prior Art
Recently, semiconductor devices have been developed to have a thinner and more miniature structure. For such semiconductor devices, there are ball grid array (BGA) semiconductor packages, chip scale semiconductor packages, and micro BGA semiconductor packages.
Also, semiconductor chips, which are mounted on semiconductor packages as mentioned above, have been developed toward a high performance of electric power circuits, an increase in operating frequency, and an expansion of circuit functions, in pace with the development of integration techniques and manufacturing equipment. For this reason, an increase in heat occurs inevitably during the operation of such a semiconductor chip.
Referring to
FIG. 10
, a typical BGA semiconductor package having a conventional structure involving the above mentioned problem is illustrated.
As shown in
FIG. 10
, the BGA semiconductor package, which is denoted by the reference numeral
100
′, includes a semiconductor chip
1
′ arranged at a central portion of the semiconductor package
100
′. The semiconductor chip
1
′ is provided with a plurality of integrated electronic circuits. A plurality of input/output pads
2
′ are provided at an upper surface of the semiconductor chip
1
′. A circuit board
10
′ is bonded at a central portion thereof to a lower surface of the semiconductor chip
1
′ by means of an adhesive
3
′.
The circuit board
10
′ includes a resin substrate
15
′. A circuit pattern
12
′ provided with bond fingers
11
′ is formed on an upper surface of the resin substrate
15
′ around the semiconductor chip
1
′. Another circuit pattern provided with a plurality of ball lands
13
′ is formed on a lower surface of the resin substrate
15
′. Each of the circuit patterns is comprised of a thin film made of a conductive material such as copper (Cu). These circuit patterns are interconnected together by via holes
14
′. The exposed surface portions of the circuit patterns not covered with the bond fingers
11
′ and ball lands
13
′ are coated with cover coats
16
′, respectively, so that those circuit patterns are protected from the external environment.
The input/output pads
2
′ of the semiconductor chip
1
′ are connected to the bond fingers
11
′ on the upper surface of the circuit board
10
′ by means of conductive wires
4
′, respectively. In order to protect the conductive wires
4
′ from the external environment, the upper surface of the circuit board
10
′ is encapsulated by a resin encapsulate
20
′.
The circuit board
10
′ is mounted on a mother board (not shown) in a state in which a plurality of conductive balls
40
′ are fused on the ball lands
13
′, respectively, so that it serves as a medium for electrical signals between the semiconductor chip l′ and mother board.
In the BGA semiconductor package
100
′ having the above mentioned configuration, the semiconductor chip
1
′ thereof exchanges electrical signals with the mother board via the input/output pads
2
′, conductive wires
4
′, bond fingers
11
′, via holes
14
′, ball lands
13
′, and conductive balls
40
′, respectively.
However, the above mentioned conventional BGA semiconductor package is problematic in that it has an increased thickness because the semiconductor chip is bonded to the upper surface of the circuit board having a relatively large thickness. This is contrary to the recent trend toward a miniaturization and thinness. As a result, the above mentioned semiconductor package is problematic in that it cannot be applied to a variety of miniature electronic appliances such as portable phones, cellular phones, pagers, and notebooks.
Furthermore, in spite of the increasing heat generated at the semiconductor chip, as mentioned above, there is no appropriate heat discharge means in the conventional semiconductor package. As a result, the conventional semiconductor package is implicated in a heat-related degradation in the electrical performance and other functions of the semiconductor chip. In severe cases, the semiconductor package and the electronic appliance using it may be so damaged as not to be inoperable.
Although a semiconductor package has been proposed, which is provided with a heat discharge plate or heat sink for easily discharging heat generated from the semiconductor chip, the provision of such a heat discharge plate causes another problem because it serves to further increase the thickness of the semiconductor package while increasing the manufacturing costs.
SUMMARY OF THE INVENTION
Therefore, the present invention has been made in view of the above mentioned problems involved in the prior art, and an object of the invention is to provide a semiconductor package having a super-thin structure and a method for fabricating the semiconductor package.
Another object of the invention is to provide a semiconductor package having a structure capable of easily discharging heat from a semiconductor chip included therein, and a method for fabricating the semiconductor package.
In accordance with one aspect, the present invention provides a semiconductor package comprising: a semiconductor chip having a first major surface and a second major surface, the semiconductor chip being provided at the second major surface with a plurality of input/output pads; a circuit board including a resin substrate having a first major surface and a second major surface, a first circuit pattern formed at the first major surface and provided with a plurality of ball lands, a second circuit pattern formed at the second major surface and provided with a plurality of bond fingers connected with the ball lands by conductive via holes, cover coats respectively coating the first and second circuit patterns while allowing the bond fingers and the ball lands to be open, and a central through hole adapted to receive the semiconductor chip therein; electrical connection means for electrically connecting the input/output pads of the semiconductor chip with the bond fingers of the circuit board, respectively; a resin encapsulate for encapsulating the semiconductor chip, the electrical connection means, and the circuit board; and a plurality of conductive balls fused on the ball lands of the circuit board, respectively.
The semiconductor chip may be arranged in such a fashion that it is oriented, at the second major surface thereof, in the same direction as the second major surface of the circuit board provided with the bond fingers while being flush, at the first major surface thereof, with the first major surface of the circuit board provided with the ball lands and one surface of the resin encapsulate.
The resin encapsulate may be formed to completely or partially encapsulate the second major surface of the circuit board provided with the bond fingers.
The second major surface of the circuit board provided with the bond fingers may be further provided with a plurality of ball lands.
A plurality of conductive balls may be fused on the ball lands provided at the second major surface of the circuit board, respectively.
The semiconductor package may further comprises a closure member attached to the first major surface of the semiconductor chip and adapted to cover the through hole of the circuit board.
Preferably, each of the closure members comprises an insulating tape or a copper layer.
In accordance with another aspect, the present invention provides a method for fabricating semiconductor packages comprising the steps of: preparing a circuit board strip including a plurality of unit circuit boards, the circuit board strip having a plurality of ball lands formed at a first major surface thereof, a plurality of bond fingers formed at a secon

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