Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...
Reexamination Certificate
2000-06-16
2004-05-04
Everhart, Caridad (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With peripheral feature due to separation of smaller...
C257S786000, C257S707000, C438S106000, C438S113000
Reexamination Certificate
active
06730989
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to semiconductor packages and to modules having such packages.
As is known in the art, semiconductor packing is typically performed by forming a plurality of identical integrated circuit chips on a semiconductor wafer. Also formed on the wafer during the fabrication of the chips is a plurality of scribe lines, or kerfs, which separate the chips. The integrated circuit chip definition is essentially complete at this wafer processing level. Some modification using electrical or laser fusing is possible such as spare, or redundant element replacement and circuit parameter (e.g., resistance) trimming, but this is limited to electrical elements with a single chip.
The wafer is then tested. The individual chips are then diced (i.e., separated) by scribing and breaking along the scribe lines. The now separated chips are individually packaged, re-tested, and sold as individual packaged chips. Typically, these individually packaged chips are mounted to a printed circuit board (PCB). For example, when the chips are Dynamic Random Access Memories (DRAMs), the individual packaged chips are mounted to a PCB to provide a memory module, such as a Single In-Line Memory Module (SIMM), Dual In-Line Memory Module (DIMM), or Rambus In-Line Memory Module (RIMM).
As is also known in the art, a DRAM chip typically includes two regions: memory array regions; and, non-memory array regions. These non-memory array regions are generally referred to as regions peripheral to the array regions or merely as peripheral regions. More particularly, referring to
FIG. 1
, a semiconductor wafer
10
is shown having a plurality of identical semiconductor chips
12
. The fabricated chips
12
are then separated along the scribe lines
14
. The borders of the scribe lines
14
shown more clearly in FIG.
2
and are designated as
14
a
,
14
b
, such
FIG. 2
showing a portion of the wafer
10
shown in FIG.
1
. Thus, an exemplary one of the chips
12
is shown in detail in
FIG. 2
to include memory array regions, here four memory array regions
16
and peripheral regions
17
. Each array region
16
includes the DRAM memory cells and associated row and column decoders, not shown. The peripheral regions
17
typically include decoders and sense amplifiers, not shown. Also included in the peripheral region
17
of each chip
12
is, in this example, a pair of voltage generators
20
. Also disposed in the peripheral regions
17
are power busses
22
which electrically interconnect the voltage generators
20
to the array regions
16
. In a conventional DRAM semiconductor chips, the voltage generators
20
occupy up to several percent of the total chip
12
.
SUMMARY OF THE INVENTION
In accordance with the present invention, a semiconductor package is provided. The package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon. The chips have separating regions between them. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes an electrical conductor to electrically connect the plurality of electrical contacts electrically interconnecting such chips with portions of the electrical conductor spanning the separating regions between the chips in the fractional portion of the wafer.
With such an arrangement, rather than have each individual chip in a separate package, the chips are designed for module granularity enabling the entire fractional portion of the wafer (i.e., portions thereof which are not used in the circuitry of the individual chips) to be utilized in an optimum manner.
In accordance with one embodiment, a semiconductor package is provided. The package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon. The chips have separating regions between them. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric having an electrical conductor thereon. The electrical conductor electrically connects the plurality of electrical contacts to electrically interconnect such chips with portions of the electrical conductor spanning the separating regions between the chips in the fractional portion of the wafer.
In accordance with the present invention, a semiconductor package is provided. The package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon. The chips have separating regions between them. Peripheral electrical components are disposed in the separating regions. The package also includes an electrical conductor to electrically connect the plurality of electrical contacts to electrically interconnect such chips with peripheral electrical components
In accordance with one embodiment of the invention, a semiconductor memory is provided. The memory includes a fractional portion of a semiconductor wafer. The fractional portion of the wafer has a plurality of integrated circuit chips. Each one of such chips has a memory array region. The chips have separating regions between them. A periphery electrical component is disposed on the fractional portion of the wafer in one of the separating regions An electrical interconnect is provided for electrically connecting the chip to the periphery electrical component.
With such an arrangement, the periphery components are added to the memory in a more efficient manner as compared to a module having only a single integrated circuit memory chip. Several benefits of this efficiency are: an averaging of elements to reduce variations; sharing of chip elements to increase the number of chips per wafer; selecting circuit options; and, wiring across the chips within the module.
In accordance with another embodiment of the invention, a semiconductor memory package is provided having a fractional portion of a semiconductor wafer. The fractional portion of the wafer has a plurality of integrated circuit chips. Each one of such chips has a memory array region. The chips have separating regions therebetween. A periphery electrical component is disposed in one of the separating regions. An electrical interconnect is provided for electrically connecting the chip to the peripheral electrical component.
In accordance with another embodiment of the invention, a semiconductor packaging arrangement, or module, is provided. The module includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer. A connector is provided for electrically connecting the electrical conductor of the package to the electrical interconnect of the printed circuit board. In accordance with another embodiment of the invention, a semiconductor memory is provided having a fractional portion of a semiconductor wafer. The fractional portion has a plurality of integrated circuit chips. Each one of such chips has a memory array region. The chips have separating regions therebetween. A periphery electrical component is disposed in one of the separating regions. An electrical interconnect electrically connects the chips to the periphery electrical component.
With such an arrangement, the same periphery electrical component is shared by the chips.
In accordance with still another embodi
Frankowsky Gerd
Kiehl Oliver
Killian Mike
Mueller Gerhard
Reithinger Manfred
Everhart Caridad
Slater & Matsil LLP
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